STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment

Kim, Jeongbin; Song, Yongwoon; Cho, Kyungseon; Lee, Hyukjun; Yoon, Hongil; Chung, Eui-Young

doi:10.1109/tcad.2021.3091440

Cited by 3 publications

(3 citation statements)

References 32 publications

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“…All the MTJs present in the C ckt and S ckt are reconfigurable whose state can dynamically be changed using the write circuit. This is in contrast to the conventional multi-context architecture [42], where either the right branch or left branch is composed of fixed MTJs serving as reference resistance. Such a modification is done to achieve a higher ∆ and read margin by storing all input operands using MTJs in the left branch and their complements in the right branch instead of fixing a reference resistance in the right branch yielding less ∆.…”

Section: A 1-bit Magnetic Adder Designmentioning

confidence: 90%

“…Multicontext or multiple bits hybrid logic architecture (Fig. 1 (A)) has multiple non-volatile cells forming a configuration plane for fast switching between contexts [22], [42]. Such an architecture facilitates the simultaneous usage of memory cells as computational and storage similar to [41] by controlling the enable signals, En1 to EnN (here, N is a natural number) corresponding to the NMOS switch block (MOS L 1-MOS L N & MOS R 1-MOS R N) effectively.…”

Section: B Multi-context Hybrid Cmos/mtj Lim Architecturementioning

confidence: 99%

“…Figs.3,4,5 show the S ckt -design 1, C ckt and S ckt -design 2, respectively, where the conventional multi-context hybrid CMOS/MTJ structure [42] is modified to achieve adder functionality along with full non-volatility. Here, unlike in [8]- [11] 1-bit of data is stored/represented by a single MTJ, instead of a pair of complementary MTJs.…”

Section: A 1-bit Magnetic Adder Designmentioning

confidence: 99%

See 2 more Smart Citations

A Fully Non-Volatile Reconfigurable Magnetic Arithmetic Logic Unit Based on Majority Logic

Rangaprasad,

Joshi

2023

IEEE Access

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Spintronics has been garnering great success in resolving the shortcomings of conventional charge-based electronics and von-Neumann architecture by offering novel computational paradigms almost devoid of leakage effects and volatility issues of traditional CMOS systems. Especially, hybrid CMOS/MTJ circuits integrating all benefits of spintronics with well-evolved CMOS technology have been extensively investigated as candidates for building next-generation processors. Motivated by the importance of magnetic processors, in this work, a novel fully non-volatile reconfigurable magnetic arithmetic logic unit (NVR-MALU) based on majority logic has been proposed. This paper encompasses the prospects of NVRMALU at both the architecture level and circuit level by discussing multi-context hybrid CMOS/MTJ LIM architecture and operation of the circuit. Furthermore, the simulation results of the proposed fully non-volatile reconfigurable magnetic full adder (NVRMFA) making up NVRMALU reveal a remarkable total power reduction by around six to forty-seven folds compared to its contemporary magnetic full adders (MFAs) discussed here. Also, NVRMALU is superior to double pass transistor clocked CMOS (DPTLCMOS) ALU in terms of power reduction by six times, thus qualifying it as an excellent normally OFF, Instant ON digital system. A four-bit extension of NVRMALU has been presented as a sign of the feasibility of the design for multi-bit applications. The transient analysis demonstrates nonvolatile and dynamic reconfigurable traits of NVRMALU in addition to functionality verification. Additionally, variability analysis has been performed to study the factors controlling read and write performances of hybrid circuits from a device-level perspective.

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Section: A 1-bit Magnetic Adder Designmentioning

confidence: 90%

Section: B Multi-context Hybrid Cmos/mtj Lim Architecturementioning

confidence: 99%

Section: A 1-bit Magnetic Adder Designmentioning

confidence: 99%

See 1 more Smart Citation

A Fully Non-Volatile Reconfigurable Magnetic Arithmetic Logic Unit Based on Majority Logic

Rangaprasad,

Joshi

2023

IEEE Access

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Energy-Efficient Power Analysis Attack Resilient Adiabatic MTJ-Based Nonvolatile CLB

Nasab,

Yang,

Thapliyal

2024

2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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MRAM-Based FPGAs: A Survey

Chandarana¹,

Elbtity²,

DeMara³

et al. 2024

Computer Memory and Data Storage

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Over the last decade, field programmable gate arrays (FPGAs) have embraced heterogeneity in a transformative way by leveraging emerging memory devices along with conventional CMOS-based devices to realize technology-specific benefits. Memristive device technologies exhibit desirable characteristics such as non-volatility, scalability, near-zero leakage, radiation hardness, and more, making them promising alternatives for SRAM cells found in conventional SRAM-based FPGAs. In recent years, a significant amount of research has been performed to take advantage of these emerging technologies to develop fundamental building blocks of FPGAs like hybrid CMOS-memristive look-up tables (LUTs) and configurable logic blocks (CLBs). In this chapter, we will provide a brief overview of the previous work on hybrid CMOS-memristive FPGAs and their corresponding opportunities and challenges.

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STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment

Cited by 3 publications

References 32 publications

A Fully Non-Volatile Reconfigurable Magnetic Arithmetic Logic Unit Based on Majority Logic

A Fully Non-Volatile Reconfigurable Magnetic Arithmetic Logic Unit Based on Majority Logic

Energy-Efficient Power Analysis Attack Resilient Adiabatic MTJ-Based Nonvolatile CLB

MRAM-Based FPGAs: A Survey

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