Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond

Chen, X.; Fang, S.; Gao, Wenli; Dyer, T.; Teh, Young Way; Tan, Shuai; Ko, Yoshinori; Baiocco, Christopher; Ajmera, A.; Park, J.; Kim, J.; Stierstorfer, R.; Chidambarrao, D.; Luo, Zongzi; Nivo, N.; Nguyen, P.; Yuan, Jun; Panda, Siddhartha; Kwon, Oh Jung; Edleman, N. L.; Tjoa, T.; Widodo, J.; Belyansky, M.; Sherony, M.; Amos,

doi:10.1109/vlsit.2006.1705216

Cited by 24 publications

(22 citation statements)

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“…Note that the L gate of the strained device needs to be the same in order to keep similar strain in the channel. This is because the channel strain is gate-length dependent in process-induced strain silicon devices [10]- [13]. From Fig.…”

Section: Devices and Measurementmentioning

confidence: 98%

Investigation and Analysis of Mismatching Properties for Nanoscale Strained MOSFETs

Kuo

Chen

2010

IEEE Trans. Nanotechnology

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This paper investigates and analyzes the matching properties of nanoscale strained MOSFETs under various bias conditions. Through a comprehensive comparison between coprocessed strained and unstrained PMOSFETs, the impact of processinduced uniaxial strain on the matching performance of MOS devices has been assessed and analyzed. Our examination indicates that, in the low-gate-voltage-overdrive (|V gst |) regime, the normalized drain current mismatch (σ(∆I d )/I d ) of the strained device is almost the same as that of the unstrained one at a given transconductance to drain current ratio (g m /I d ). In the high |V gst | linear regime, the σ(∆I d )/I d for the strained device is smaller than that of the unstrained one because of its smaller normalized current factor mismatch. In the high |V gst | saturation regime, the improvement in the σ(∆I d )/I d for the strained device is further enhanced because of the reduced critical electric field at which the carrier velocity becomes saturated.

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Section: Devices and Measurementmentioning

confidence: 98%

Investigation and Analysis of Mismatching Properties for Nanoscale Strained MOSFETs

Kuo

Chen

2010

IEEE Trans. Nanotechnology

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“…The amount of improvement is dependent on the stress liner used and the space width as well. For a 45-nm CMOS technology, a 20% improvement of pMOS performance is observed for SPT when the same compressive nitride liner is used, while nMOS is improved by 3% [37]. The most critical process of SPT is the RIE used for spacer removal.…”

Section: Stress Proximity Technique (Spt)mentioning

confidence: 99%

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Yang

Cai

2011

Sci. China Inf. Sci.

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The introduction and advancement of strain engineering has been one of the most critical features for the state-of-the-art nanoscale CMOS transistors. This paper provides an overview of the major strain engineering techniques that have remarkably re-shaped the advanced CMOS transistor architecture, including embedded SiGe (eSiGe), embedded Si:C (eSi:C), stress memorization technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT). The advent of high-K/metal-gate (HKMG) also brings in additional strain benefit with its metal gate stressor (MGS) and replacement gate (RMG) process. Strain engineering continues to evolve and will remain to be one of the key performance enablers for the future generation of CMOS technologies. CitationYang B, Cai M. Advanced strain engineering for state-of-the-art nanoscale CMOS technology. Sci China Inf Sci, 2011, 54: 946-958,

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“…DSL (i.e. a tensile nitride layer over the nMOSFET and a compressive nitride later over the pMOSFET) improves the drive currents of ''n'' and ''p'' MOSFETs (Chen 2006). Another way of introducing a local strain in the device is through stress memorisation technique (SMT) (Ortolland 2006).…”

Section: Introductionmentioning

confidence: 99%

Effect of STI, DSL and SMT onf_Tand noise-figure in 30 nm gate length NMOSFET

Srinivasan¹,

Saha²

2008

International Journal of Electronics

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The effect of stress, in particular, shallow trench isolation, dual stress liner (DSL) and stress memorisation technique (SMT) on unity gain cut-off frequency (f T ) and noisefigure (NF) of 30 nm gate length nMetal-oxide-semiconductor field-effect transistors (nMOSFET) has been studied, using extensive process and device simulations. The simulations include many of the latest process steps, like high-K dielectric, metal gate, laser annealing and stress engineering aspects. The results have been compared with the hypothetical MOSFET where the device is set to be stress-free. Simulation results show that DSL improves both f T and NF whereas SMT technique improves f T and degrades the noise performance.

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Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond

Cited by 24 publications

References 0 publications

Investigation and Analysis of Mismatching Properties for Nanoscale Strained MOSFETs

Investigation and Analysis of Mismatching Properties for Nanoscale Strained MOSFETs

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Effect of STI, DSL and SMT onf_Tand noise-figure in 30 nm gate length NMOSFET

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Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond

Cited by 24 publications

References 0 publications

Investigation and Analysis of Mismatching Properties for Nanoscale Strained MOSFETs

Investigation and Analysis of Mismatching Properties for Nanoscale Strained MOSFETs

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Effect of STI, DSL and SMT onfTand noise-figure in 30 nm gate length NMOSFET

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Product

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Effect of STI, DSL and SMT onf_Tand noise-figure in 30 nm gate length NMOSFET