Stress-Induced Hump Effects of p-Channel Polycrystalline Silicon Thin-Film Transistors

Huang, Chih‐Fen; Peng, C.-Y.; Yang, Yihan; Sun, Haiyan; Chang, Hern-Jia; Kuo, P.-S.; Chang, Herng-Hua; Liu, Chee-Zxaing; C, Liu

doi:10.1109/led.2008.2007306

Cited by 66 publications

(29 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Because the firststage degradation is actually suppressed (instead of activated) by the stress temperature, the extracted energy of ∼0.07 eV is called deactivation energy (E da ). Such an energy value is typical for the energy required for electrons detrapping from the gate oxide through the Frenkel-Poole emission mechanism [20], [28]. Whereas for the second-stage degradation, activation energy (E a ) of ∼0.5 eV is extracted, which is consistent with the energy required to break Si-H bonds and generate traps [29].…”

Section: A Degradation Behaviorssupporting

confidence: 63%

Two-Stage Degradation of p-Type Polycrystalline Silicon Thin-Film Transistors Under Dynamic Positive Bias Temperature Stress

Zhang

Wang

2014

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

Two-stage degradation of p-type polycrystalline silicon thin-film transistors under dynamic positive bias temperature (PBT) stress is reported for the first time. ON-state current (I ON ) gradually increases in the first degradation stage while dramatically drops in the second degradation stage, which are, respectively, due to the channel length shortening effect, caused by electrons trapping into the gate oxide, and grain boundary potential barrier buildup, caused by dynamic hotcarrier-induced traps generation. The transition from the first to the second degradation stage is clarified, in which the pulse peak duration plays a key role. Longer pulse peak duration is preferred to suppress the dynamic PBT stress-induced degradation.Index Terms-Dynamic stress, hot carrier (HC), impact ionization, poly-Si, positive bias temperature instability (PBTI), thin-film transistor (TFT).

show abstract

Section: A Degradation Behaviorssupporting

confidence: 63%

Two-Stage Degradation of p-Type Polycrystalline Silicon Thin-Film Transistors Under Dynamic Positive Bias Temperature Stress

Zhang

Wang

2014

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

show abstract

“…In poly-Si TFTs with top gate structure, the stress-induced hump was reported by the generation of the parasitic transistor as a result of the high electric field due to thinner insulator thickness at the active edge along the channel width direction [12]. In this works, however, the device has bottom gate structure where the gate insulator was formed after the gate patterning and so the parasitic transistor formation in the active edge was difficult.…”

Section: Resultsmentioning

confidence: 95%

Anomalous Stress-Induced Hump Effects in Amorphous Indium Gallium Zinc Oxide TFTs

Kim¹,

Jeong²,

Yun³

et al. 2012

Transactions on Electrical and Electronic Materials

View full text Add to dashboard Cite

In this paper, we investigated the anomalous hump in the bottom gate staggered a-IGZO TFTs. During the positive bias stress, a positive threshold voltage shift was observed in the transfer curve and an anomalous hump occurred as the stress time increased. The hump became more serious in higher gate bias stress while it was not observed under the negative bias stress. The analysis of constant gate bias stress indicated that the anomalous hump was influenced by the migration of positively charged mobile interstitial zinc ion towards the top side of the a-IGZO channel layer.

show abstract

“…Instabilities observed in AOS devices, include the parallel displacement of the transfer curves observed in all TFTs, V T shift, as well as a hump or deformation which can appear in the subthreshold region of the transfer curves, after illumination and DC stress [4,5]. The presence of a similar deformation in the transfer curves, not related to stressing conditions, has been observed in other TFTs and conditions, as for example in p and n-type polycrystalline TFTs [6]. More recently it was shown by simulation that in TFTs with thick active layer, higher than 120 nm thick, the deformation in the transfer curve was observed, [7].…”

Section: Amorphousmentioning

confidence: 72%

Simulation of the bias stress-induced hump, observed in the transfer characteristic of Amorphous Oxide Thin-Film Transistors

Estrada

Cerdeira

Iñı́guez

2012

2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)

View full text Add to dashboard Cite

The deformation in the subthreshold region of the transfer characteristic observed in Amorphous Oxide Semiconductor (AOS) Thin-Film Transistors (TFTs) is simulated, analyzing its origin. We show that, when the density of positively charged states at the back interface between the active and the passivation layer becomes sufficiently high, a parallel current path is formed between drain and source at the back of the structure. This leakage current gives rise to a deformation or hump in the transfer curve. During DC bias stress, the density of charged back interface states can increase due to carrier trapping or trap creation, depending on the intensity and time duration of the applied gate bias, as well as on the materials of the passivation layer and fabrication conditions of the devices. This explanation is in agreement with experimental data for AOS TFTs.

show abstract

Stress-Induced Hump Effects of p-Channel Polycrystalline Silicon Thin-Film Transistors

Cited by 66 publications

References 14 publications

Two-Stage Degradation of p-Type Polycrystalline Silicon Thin-Film Transistors Under Dynamic Positive Bias Temperature Stress

Two-Stage Degradation of p-Type Polycrystalline Silicon Thin-Film Transistors Under Dynamic Positive Bias Temperature Stress

Anomalous Stress-Induced Hump Effects in Amorphous Indium Gallium Zinc Oxide TFTs

Simulation of the bias stress-induced hump, observed in the transfer characteristic of Amorphous Oxide Thin-Film Transistors

Contact Info

Product

Resources

About