Strategy for Selective Printing of Gate Insulators Customized for Practical Application in Organic Integrated Devices

Abstract

Direct drawing techniques have contributed to the ease of patterning soft electronic materials, which are the building blocks of analog and digital integrated circuits. In parallel with the printing of semiconductors and electrodes, selective deposition of gate insulators (GI) is an equally important factor in simplifying the fabrication of integrated devices, such as NAND and NOR gates, and memory devices. This study demonstrates the fabrication of six types of printed GI layers (high/low-k polymer and organic–inorganic hybrid material), which are utilized as GIs in organic field-effect transistors (OFETs), using the electrostatic-force-assisted dispensing printing technique. The selective printing of GIs on the gate electrodes enables us to develop practical integrated devices that go beyond unit OFET devices, exhibiting robust switching performances, non-destructive operations, and high gain values. Moreover, the flexible integrated devices fabricated using this technique exhibit excellent operational behavior. Therefore, this facile fabrication technique can pave a new path for the production of practical integrated device arrays for next-generation devices.

Engineering Aggregation‐Resistant MXene Nanosheets As Highly Conductive and Stable Inks for All‐Printed Electronics

“…In addition, it possesses high dielectric constant (≈13), and can diminish ferroelectric property, the character of PVDF‐HFP, by reducing its crystallinity, which leads to low voltage and hysteresis‐free TFT operation. [ 40 ] The combination of sCNT, FPVDF‐HFP, MXene makes it possible to fabricate high performance TFT and circuits with simple printing method. The EHD printing successfully produced continuous lines of MXene nanosheets and sCNT networks, as SEM images shown in Figure S13, Supporting Information.…”

Mass-Synthesized Solution-Processable Polyimide Gate Dielectrics for Electrically Stable Operating OFETs and Integrated Circuits

“…However, the voltage level of these logic gates was relatively high (~40 V), and this point can be a disturbing part for the industrialization of OFETs base PI layers. However, it can be improved if device geometry is improved, such as by applying short channel devices through photolithographic processes usually used in industry and high-k insulating materials that together can maintain high capacitance values [5,33]. Considering the results, this study showed the driving stability of OFETs with PI gate insulators, which were fabricated through factory methods.…”

“…Figure 2a shows AFM images of the prepared PI layers. The AFM image exhibited a smooth amorphous surface with a root-mean-square (RMS) roughness value of 0.212 nm, and this low RMS roughness value of less than 0.5 nm can provide a favorable environment for the growth of organic semiconducting crystals [5,19,20]. Furthermore, in order to identify the possibility of using this PI thin film as a dielectric layer for OFETs, the electrical characteristics were evaluated by fabricating a metal-insulator-metal (MIM)-structured capacitor with Al and thermally prepared PI layers (thickness: 150 nm) on Si/SiO 2 wafers.…”

“…Compared with conventional inorganic-based dielectric materials employed in the modern electronic industry, polymeric dielectrics are capable of providing excellent mechanical flexibility, good solution processability, and better compatibility with various types of substrates and organic channel materials [3,4]. Additionally, interface engineering with polymeric dielectrics, such as surface treatment on inorganic insulators, can offer potential capabilities for optimizing the molecular arrangements of organic semiconductors and trap-free interfaces for efficient charge transport, [2,5,6] influencing their compatibility with microfabrication technologies for highly integrated practical applications [5,7].…”

Electrohydrodynamic‐Printed Polyvinyl Alcohol‐Based Gate Insulators for Organic Integrated Devices

“…Especially for integrating organic electronic circuits using bottom‐gate OFETs, a local coating and patterning of the gate dielectric layer are commonly required for fully covering the gate electrodes where input voltages are applied. [ 12 ] Therefore, a facile EHD technique should be exploited for the preparation of gate insulators (GIs) in low‐cost and large‐area circuit manufacturing.…”