Strained-SOI n-Channel Transistor With Silicon–Carbon Source/Drain Regions for Carrier Transport Enhancement

Chui, King-Jien; Ang, Kah‐Wee; Chin, Hock-Chun; Chen, Shen; Wong, Lingkai; Tung, Chih-Hang; Balasubramanian, N.; Li, Ming Fu; Samudra, Ganesh S.; Yeo, Yee-Chia

doi:10.1109/led.2006.881083

Cited by 20 publications

(11 citation statements)

References 8 publications

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“…1,2) A top stressor, such as a highstress silicon nitride film formed over a transistor structure, has also been employed to enhance the electron mobility. 3,4) Recently, silicon-on-insulator (SOI) NMOSFETs with silicon-carbon (SiC) alloy source/drain (S/D) regions have been demonstrated, [5][6][7] whereas relatively little is known about the stress effects in devices i.e., the magnitude and distribution of stress components and the origin of the stress field, and their relationship to electron mobility enhancement. In the present paper, we perform a theoretical evaluation of the stress field in the channel of a SOI NMOSFET with lateral lattice-mismatched SiC source/ drain (S/D) stressors.…”

Section: Introductionmentioning

confidence: 99%

Impact of Source/Drain Si_1-yC_y Stressors on Silicon-on-Insulator N-type Metal–Oxide–Semiconductor Field-Effect Transistors

Lin

Chang

Huang

et al. 2007

jjap

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The stress field in the channel of a silicon-on-insulator (SOI) N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) with silicon-carbon alloy source and drain stressors was evaluated. The physical origin of the stress components in the transistor channel region was explained. The magnitude and distribution of the strain components, and their dependence on device design parameters such as the spacing between the silicon-carbon alloy stressors, the carbon mole fraction in the stressors and stressor recessed depth and raised height were investigated. The reduction in the stressor spacing or increase in the carbon mole fraction of the stressors and the stressor recessed depth and raised height increase the magnitude of the vertical compressive stress and the lateral tensile stress in the portion of the channel region where the inversion charge exists. This is beneficial for improving the electron mobility in NMOSFETs. A simple guiding principle for an optimum combination of the above-mentioned device design parameters and the trade-off between performance and junction leakage current degradation is discussed in this paper.

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Section: Introductionmentioning

confidence: 99%

Impact of Source/Drain Si_1-yC_y Stressors on Silicon-on-Insulator N-type Metal–Oxide–Semiconductor Field-Effect Transistors

Lin

Chang

Huang

et al. 2007

jjap

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“…Recently, Si:C embedded in the source and drain (e-Si:C S/D) technology for improving nMOSFET drive current has been reported. [1][2][3][4][5][6][7] Since the lattice constant of Si:C is smaller than that of Si, e-Si:C S/D can induce tensile stress in channels 1,4,8) and improve the electron mobility of nMOSFETs. A small [C] sub within 1-2% is required to induce significant strain.…”

Section: Introductionmentioning

confidence: 99%

“…A widely used approach to forming e-Si:C S/D is to recess S/D by etching and then deposit strained Si:C films using selective epitaxial growth, which requires a complicated process integration. 1,2,5,6) In contrast, the combination of C implantation and annealing enables a relatively simple process integration to form e-Si:C S/D. 4,9) However, owing to the extremely low solid solubility of C in Si (3:5 Â 10 17 cm À3 at the melting point), it is difficult to grow strained Si:C films with [C] sub > 1%.…”

Section: Introductionmentioning

confidence: 99%

Carbon Incorporation into Substitutional Silicon Site by Molecular Carbon Ion Implantation and Recrystallization Annealing as Stress Technique in n-Metal–Oxide–Semiconductor Field-Effect Transistor

Itokawa

Miyano

Oshima

et al. 2010

Jpn. J. Appl. Phys.

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Since the lattice constant of silicon-carbon (Si:C) is smaller than that of Si, Si:C embedded in the source and drain (e-Si:C S/D) can induce tensile stress in the channel and improve the electron mobility of n-metal–oxide–semiconductor field-effect transistor (nMOSFETs). In this research, molecular carbon (C) ion implantation and recrystallization schemes employed to achieve strained Si:C films with a high substitutionally incorporated carbon concentration ([C]sub) and a high ratio of substitution were studied. Several recrystallization techniques including rapid-thermal-annealing (RTA)-based solid phase epitaxy (SPE), spike annealing, and nonmelt laser annealing have been used to optimize C incorporation into Si and strain application. Results of these different implantation and annealing techniques are compared and discussed. Furthermore, we proposed the first recrystallization by nonmelt laser annealing and the co-incorporation of a dopant that increases the rate of Si regrowth and has a covalent radius slightly different from that of Si. These processes markedly promoted the recrystallization of C densely incorporated in an amorphous Si layer and improved the crystallinity of strained Si:C films while maintaining a high [C]sub at a high ratio of substitution.

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“…[1][2][3][4][5][6][7] High stress CAESL causes strain generated in silicon underneath MOSFET gate oxide, which affects carrier mobility depending on the stress type of CAESL SiN. Tensile stress enhances electron mobility, thus improves Ntype MOSFET (NMOSFET) I on -I off performance; whereas compressive stress enhances hole mobility, thus improves P-type MOSFET (PMOSFET) I on -I off performance.…”

Section: Introductionmentioning

confidence: 99%

“…Continuous device shrinkage beyond 45 nm requires using higher stress silicon nitride (SiN) as contact etch stop layer (CAESL) to increase metal oxide semiconductor field effect transistor (MOSFET) carrier mobility to improve device performance. [1][2][3][4][5][6][7] High stress CAESL causes strain generated in silicon underneath MOSFET gate oxide, which affects carrier mobility depending on the stress type of CAESL SiN. Tensile stress enhances electron mobility, thus improves Ntype MOSFET (NMOSFET) I on -I off performance; whereas compressive stress enhances hole mobility, thus improves P-type MOSFET (PMOSFET) I on -I off performance.…”

Section: Introductionmentioning

confidence: 99%

Stress Modulation of Silicon Nitride Film by Initial Deposition Conditions for Transistor Carrier Mobility Enhancement

Tian¹,

Zuo²,

Lü³

et al. 2010

Jpn. J. Appl. Phys.

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Various silicon nitride (SiN) films were prepared using plasma enhanced chemical vapor deposition (PECVD) by tuning deposition condition to control initial hydrogen in the films. The as-deposited films, which exhibit different tensile stress from 0.2 to 1.2 GPa, were treated by ultraviolet (UV) curing to investigate how the stress and shrinkage response to film initial hydrogen state and how to modify SiN hydrogen state by deposition condition to achieve high tensile stress. The results show that the stress and shrinkage of SiN films response quite differentially to UV curing depending on hydrogen state. Stress of SiN was hardly tuned by UV curing in case of Si-H deficiency, but largely increased in case of balanced Si-H and N-H bonds. Both high and low stress-tunable SiN films were used as contact etch stop layer (CAESL) in 45 nm bulk device. Device performance (I on -I off ) has been improved by about 5% using high stress-tunable SiN film. #

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Strained-SOI n-Channel Transistor With Silicon–Carbon Source/Drain Regions for Carrier Transport Enhancement

Cited by 20 publications

References 8 publications

Impact of Source/Drain Si_1-yC_y Stressors on Silicon-on-Insulator N-type Metal–Oxide–Semiconductor Field-Effect Transistors

Impact of Source/Drain Si_1-yC_y Stressors on Silicon-on-Insulator N-type Metal–Oxide–Semiconductor Field-Effect Transistors

Carbon Incorporation into Substitutional Silicon Site by Molecular Carbon Ion Implantation and Recrystallization Annealing as Stress Technique in n-Metal–Oxide–Semiconductor Field-Effect Transistor

Stress Modulation of Silicon Nitride Film by Initial Deposition Conditions for Transistor Carrier Mobility Enhancement

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Strained-SOI n-Channel Transistor With Silicon–Carbon Source/Drain Regions for Carrier Transport Enhancement

Cited by 20 publications

References 8 publications

Impact of Source/Drain Si1-yCy Stressors on Silicon-on-Insulator N-type Metal–Oxide–Semiconductor Field-Effect Transistors

Impact of Source/Drain Si1-yCy Stressors on Silicon-on-Insulator N-type Metal–Oxide–Semiconductor Field-Effect Transistors

Carbon Incorporation into Substitutional Silicon Site by Molecular Carbon Ion Implantation and Recrystallization Annealing as Stress Technique in n-Metal–Oxide–Semiconductor Field-Effect Transistor

Stress Modulation of Silicon Nitride Film by Initial Deposition Conditions for Transistor Carrier Mobility Enhancement

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Impact of Source/Drain Si_1-yC_y Stressors on Silicon-on-Insulator N-type Metal–Oxide–Semiconductor Field-Effect Transistors

Impact of Source/Drain Si_1-yC_y Stressors on Silicon-on-Insulator N-type Metal–Oxide–Semiconductor Field-Effect Transistors