Strained SiGe Channels for Band-Edge PMOS Threshold Voltages With Metal Gates and High- $k$ Dielectrics

Gilmer, D. C.; Schaeffer, J.; Taylor, William J.; Capasso, C.; Junker, K.; Hildreth, J.; Tekleab, D.; Winstead, B.; Samavedam, S.

doi:10.1109/ted.2010.2041866

Cited by 27 publications

(15 citation statements)

References 19 publications

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“…cSiGe has been proposed as a pFET channel material [1][2][3][4] to reduce the threshold voltage (V TH ). The V TH reduction is achieved by narrowing of the channel band-gap, on the valence band side, with addition of Ge to Silicon(Si).…”

Section: Introductionmentioning

confidence: 99%

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A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Krishnan

Kwon²,

Moumen³

et al. 2011

2011 International Electron Devices Meeting

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Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-κ/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with T inv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.Introduction:

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Section: Introductionmentioning

confidence: 99%

“…IBM SRDC, 1 Toshiba America Electronic Components Inc., 2 GLOBALFOUNDRIES, 3 Samsung Electronics, 4 Infineon Technologies, 5 Abstract:…”

mentioning

confidence: 99%

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Krishnan

Kwon²,

Moumen³

et al. 2011

2011 International Electron Devices Meeting

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“…The mobility can be degraded when the negative piezoresistance coefficient of the transverse [1 1 0] p-channel is beyond a critical W/L ratio. Nevertheless, the critical W/L ratio may require further verification because of other factors reported in literature, such as the capsulated Si (capsulated silicon) thickness [8] and the Ge-content Si 1Àx Ge x [2,9], which can be sensitive to the device performance. In addition, a high Ge content and a thick Si 1Àx Ge x have been reported with a decreased threshold voltage (V T ) [9].…”

Section: Introductionmentioning

confidence: 99%

“…Nevertheless, the critical W/L ratio may require further verification because of other factors reported in literature, such as the capsulated Si (capsulated silicon) thickness [8] and the Ge-content Si 1Àx Ge x [2,9], which can be sensitive to the device performance. In addition, a high Ge content and a thick Si 1Àx Ge x have been reported with a decreased threshold voltage (V T ) [9]. Thus, we may infer that V T shifting is correlated to the current drive (or transconductance) of a strained SiGe channel, and these V T shifting and performance enhancement or degradation can both be dimensionally dependent compared with those of a control Si channel.…”

Section: Introductionmentioning

confidence: 99%

Threshold voltage and transconductance shifting reliance on strained-SiGe channel dimension

Chang

Lin

Shih

2015

Solid-State Electronics

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“…A S THE need of the deep nanonode technology in IC manufacturing, using high-k [1]- [3] and metal gate (HK/MG) [4], [5] technologies as well as the gate-last (GL) process is a deliberate choice to increase the drive current of pMOSFET and avoid the higher source/drain annealing temperature in process integration, causing the HK crystallization and possibly increasing the risk of higher gate leakage. The advantages are not only to freely adjust the threshold voltage (V T ), but to reduce the power consumption or delay time because of the lower gate resistance in the circuit concern.…”

Section: Introductionmentioning

confidence: 99%

Gate Leakage Characteristics for 28 nm HfZrO<sub><italic>x</italic></sub> pMOSFETs After DPN Process Treatment With Different Nitrogen Concentration

Lee

Wang

et al. 2014

IEEE Trans. Plasma Sci.

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Feasibly adjusting the gate leakage and the device performance in balance is an obvious challenge. Additionally, stacking the high-k dielectric as a gate dielectric in nanonode process is an appreciate way to promote the drive current in pMOSFETs. Unfortunately, the amount of oxygen vacancy or the interfacial layer thickness on the surface channel will possibly reduce the drive current owing to the increasing magnitude of threshold voltage and increase in the gate leakage degrading the standby capability in circuit operation. To retard this disadvantage or intensify the device quality, applying a lower pressure decoupled-plasma nitridation process to obliquely reform the amount of oxygen vacancy is a feasible alternative. On the basis of tested data, the nitridation treatment in a higher N 2 concentration is better than that in a lower one, such as the improvement of gate leakage, drive current, subthreshold swing, and channel mobility in pMOSFETs, especially for shorter channel-length devices.Index Terms-Decoupled-plasma nitridation (DPN), gate dielectric, gate leakage, high-k dielectric.

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Strained SiGe Channels for Band-Edge PMOS Threshold Voltages With Metal Gates and High- $k$ Dielectrics

Cited by 27 publications

References 19 publications

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Threshold voltage and transconductance shifting reliance on strained-SiGe channel dimension

Gate Leakage Characteristics for 28 nm HfZrO<sub><italic>x</italic></sub> pMOSFETs After DPN Process Treatment With Different Nitrogen Concentration

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