SiGe/Si hetero structure has been examined using high resolution x-ray diffraction for strain and cross sectional transmission electron microscopy for implant induced defects with various p-type source drain implant conditions at room or cryogenic temperature. The implant induced end-of-range defects can be reduced by optimizing Ge pre-amorphization implant energy and at cryogenic temperature. The alleviated strain relaxation and lower junction leakage current are correlated to the cryo-implant defect reduction.For strained channel p-type metal-oxide-semiconductor (pMOS) devices, a uniaxial compressive stress in the channel is induced by the selective epitaxial growth (SEG) of embedded SiGe (eSiGe) in recessed source/drain (S/D) regions. Higher channel stress levels and lower SD resistance can be achieved by increasing the Ge content and the epilayer thickness in the S/D regions. 1 To be fully incorporated into Complimentary MOS (or CMOS) technology, these SiGe/Si layers will experience and have to withstand further processing steps, i.e. ion implantation and annealing. It is known that the subsequent spike rapid thermal process (sRTP) and Laser millisecond (msec) anneal could relax the strain by forming misfit and threading dislocations as lattices re-grown and dopants activated. 2, 3 Ion implantation creates point defects, which act as nucleation sites for relaxation induced dislocation or aid in the inter-diffusion of Boron and Ge, resulting in accelerated strain relaxation. 4-6 This leads to a lower hole mobility and higher junction leakage therefore degrading device performance.The evolution of end-of-range (EOR) defects and amorphization as a function of implant temperature have been reported previously. 7,8 The dynamic annealing process of interstitials and vacancies, generated by the implant, can be retarded by applying cryo temperature on substrate, resulting in deeper amorphization and smoother amorphous and crystal (a/c) interface layers. Cryo implants are well known to reduce Boron diffusion and activation anomalies. 7,9,10 In this paper, eSiGe SD integrated in state-of-the-art 28 nm CMOS flow is studied for strain relaxation. The strain is characterized with high resolution x-ray diffraction (HRXRD) rocking curves. The defects are examined with cross sectional transmission electron microscopy (XTEM) and correlated to the junction leakage. The modulation of injected silicon interstitial on the strain relaxation processes at the SiGe/Si interface after 1015 • C sRTP and 1250 • C Laser msec annealing, coupled with cryo temperature pMOS source and drain (PSD) implants, are investigated. The cryo-implants were conducted at −100 • C. The junction leakage related to the defect propagated from SiGe layer to Si substrate after msec anneal are discussed.The recessed SiGe S/D junction was fabricated and integrated with 28 nm device flow. 11 SiGe on Si substrate was epitaxial-grown (EPI) by low pressure chemical vapor deposition. The p/n junction was formed by in-situ doped SiGe EPI and followed with PSD implant...