Strain Reduction in Selectively Grown CdTe by MBE on Nanopatterned Silicon on Insulator (SOI) Substrates

Abstract

Silicon based substrates for the epitaxy of HgCdTe are an attractive low cost choice for monolithic integration of infrared detectors with mature Si technology and high yield. However, progress in heteroepitaxy of CdTe/Si (for subsequent growth of HgCdTe) is limited by the high lattice and thermal mismatch which creates a lot of strain at the heterointerface that results in high density of dislocations. Previously we have reported 1 theoretical modeling of strain partitioning between CdTe and Si on nanopatterned SOI substrates. In this paper, we present an experimental study of CdTe epitaxy on nanopatterned (SOI). SOI (100) substrates were patterned with interferometric lithography and reactive ion etching to form a 2-D array of silicon pillars with ~250nm diameter and 1µm pitch. MBE was used to grow CdTe selectively on the silicon nanopillars. Selective growth of CdTe was confirmed by SEM, AFM and XPS. Coalescence of CdTe on the silicon nanoislands has been observed from the SEM characterization. Selective growth was achieved with a two step growth process involving desorption of nucleation layer followed by regrowth of CdTe at a rate of 0.2Å/s. Strain measurements by Raman spectroscopy show a lower Raman shift (2.7 ± 2 cm -1 from the bulk value of 170 cm -1 ) in CdTe grown on nanopatterned SOI compared to planar silicon (Raman shift of 4.4 ± 2 cm -1 ), indicating reduced strain on the nanopatterned substrates.

Study of the Effect of Various Chemical Polishing Treatments on MBE-Grown CdTe/GaAs (211)B Heterostructures

“…We also observed that the Nakagawa etching technique eroded surface defects caused under Te rich growth conditions. Hence, we can conclude that the Nakagawa etch pits form in the regions of Te precipitates [34] while the Everson etch pits form at dislocation sites. We did not calculate any EPD value for sample B due to overlapping pits.…”