Strain enhanced low-V<inf>T</inf> CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

“….) may be relaxed by using multiple-gate devices for regular V t applications (RVT) [5,6]. This advantage is depicted in Fig.…”

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

“…The "gate-first" approach is very similar to the conventional CMOS flow with the exception that the SiON/poly Si gate-stack is replaced by a stack of HK/MG/poly Si [4]. Most existing stressors, such as eSiGe, SMT, and DSL, remain effective in improving the performance of HKMG CMOS transistors [46][47][48]. As reported in Figure 11, the 32-nm "gate first" HKMG nMOS drive current was improved by 15% due to the tensile stress liner, while the pMOS drive current was improved by 40% due to the compressive stress liner [48].…”

Physical Mechanism of Threshold Voltage Modulation by Ge Channel Ion Implantation in the TiN/HfO2 Gate Stack Systems

“…1,8) Recently, capping layer insertion at the top/bottom of high-k layers has been identified as one of the solutions for V TH tuning. [9][10][11][12][13][14] In nMOS, the use of group IIA and IIIB oxides (e.g., La, Y, and Dy) enables both V TH shift and equivalent oxide thickness (EOT) scaling simultaneously, resulting in improved transistor performance. [9][10][11][12] In pMOS, however, the range of V TH modulation by Al and Ti insertion is insufficient for achieving low-V TH transistor operation.…”

“…[9][10][11][12][13][14] In nMOS, the use of group IIA and IIIB oxides (e.g., La, Y, and Dy) enables both V TH shift and equivalent oxide thickness (EOT) scaling simultaneously, resulting in improved transistor performance. [9][10][11][12] In pMOS, however, the range of V TH modulation by Al and Ti insertion is insufficient for achieving low-V TH transistor operation. 14) An alternative method of pMOS transistor V TH tuning is the use of an epitaxial SiGe channel structure.…”

“…Strict control of capped layer etching from other types of transistors is required for the dual capping scheme, and a sophisticated Si recess/ SiGe thickness control as well as SiGe formation in only the pMOS region by hard-masked integration flow are necessary for epitaxial SiGe formation in the pMOS region. 11,12,15) On the other hand, the ion implantation (I/I) approach is an attractive method for the V TH tuning of a CMOS, 19,20) because, in this method area definition can be determined using a resist mask without complicated hard-mask processes and layer etching from unnecessary regions.…”