Strain engineering in nanoscale CMOS FinFETs and methods to optimize R&lt;inf&gt;S/D&lt;/inf&gt;

Smith, Casey; Parthasarathy, S.; Coss, Brian E.; Williams, Jason; Adhikari, Hemant; Ge, Smith; Sassman, B.; Hussain, Muhammad Mustafa; Majhi, P.; Jammy, R.

doi:10.1109/vtsa.2010.5488905

Cited by 6 publications

(7 citation statements)

References 4 publications

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“…The simulated strain values were converted from the simulated stress values by the simulator using the compliance matrix [Eq. (8)]. The simulated strain values are comparable with the measured ones in fin A.…”

Section: Resultssupporting

confidence: 72%

“…INTRODUCTION With scaling of the silicon metal-oxide-semiconductor field-effect transistor (MOSFET) into sub-20 nm technology nodes, the conventional planar device structure would be replaced by the multi-gate or fin field-effect transistor (FinFET) device structure, which has excellent control of short-channel effects (SCEs). [1][2][3][4][5][6][7][8][9][10][11] To boost the switching speed or drive current of FinFETs, carrier mobilities may be enhanced by channel strain engineering. [4][5][6][7][8][9][10][11][12][13][14][15] Recently, a new liner stressor comprising Ge 2 Sb 2 Te 5 (GST) was reported for inducing strain in p-channel FinFETs, significantly increasing the hole mobility and drive current.…”

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confidence: 99%

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Lattice strain analysis of silicon fin field-effect transistor structures wrapped by Ge2Sb2Te5 liner stressor

Ding

Cheng

et al. 2013

Journal of Applied Physics

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The local strain components in the source/drain (S/D) and channel regions of Si fin field-effect transistor (FinFET) structures wrapped around by a Ge2Sb2Te5 liner stressor were investigated for the first time using nano-beam diffraction. When the Ge2Sb2Te5 (GST) layer changes phase from amorphous to crystalline, it contracts and exerts a large stress on the Si fins. This results in large compressive strain in the S/D region of ⟨1¯10⟩-oriented Si FinFETs of up to −1.15% and −1.57% in the ⟨110⟩ (horizontal) and ⟨001⟩ (vertical) directions, respectively. In the channel region of the FinFETs under the metal gate, the GST contraction results in up to −1.47% and −0.61% compressive strain in the ⟨110⟩ and ⟨001⟩ directions, respectively. In the channel region, the ⟨110⟩ compressive strain is higher at the fin sidewalls and lower near the fin center, while the ⟨001⟩ compressive strain is lower at the sidewalls and higher near the center.

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Section: Resultssupporting

confidence: 72%

mentioning

confidence: 99%

Lattice strain analysis of silicon fin field-effect transistor structures wrapped by Ge2Sb2Te5 liner stressor

Ding

Cheng

et al. 2013

Journal of Applied Physics

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“…2(b) shows R S/D extracted from the linear intercept (L G = 0) of a total resistance (R TOT = V lin DS /I lin D ) versus L G (40 nm-1 μm) plot at different gate overdrives [19]. To account for the gateunderlap architecture, the dependence of extension resistance on gate voltage is modeled by an exponential decay function to an asymptotic value at large overdrives which is taken as R S/D [14]. The AlO x − B process has ≈25% (100 Ω · μm) lower R S/D resistance compared to the control with TaN only due to the reduced SBH from the AlO x layers.…”

Section: Resultsmentioning

confidence: 99%

“…Fig. 1(b) illustrates key changes to the FinFET baseline fabrication process made to accommodate DDM-SBH tuning layers [14]. Silicidation of the source/drain and gate contact was skipped [see step 3 in Fig.…”

Section: Device Structure and Fabricationmentioning

confidence: 99%

Contact Resistance Reduction to FinFET Source/Drain Using Novel Dielectric Dipole Schottky Barrier Height Modulation Method

Coss

Smith²,

Loh³

et al. 2011

IEEE Electron Device Lett.

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Recent experiments have demonstrated the ability to alleviate Fermi-level pinning, resulting in reduced Schottky barrier heights (SBHs) and reduced contact resistivity by inserting thin layers of dielectric at the contact interface. In this letter, FinFETs with dielectric SBH tuning layers are investigated and shown to have reduced contact resistance over the control wafer. The reduced contact resistivity results in an ≈25% increase in drive current as well as a reduction of R S/D by 100 Ω · μm. Contact chain measurement shows a 10-Ω · μm 2 reduction in specific contact resistivity over the control wafer associated with a 100-meV reduction in SBH. Routes to further improvements in device performance are discussed, including key material considerations for dielectric tuning layers. Index Terms-Contact resistance, FinFETS, semiconductorinsulator interfaces, semiconductor-metal interfaces.A CCORDING to the International Technology Roadmap for Semiconductors [1], one of the key challenges in the coming technology nodes is parasitic external resistance of which contact resistivity is the largest component. In order to scale both traditional planar bulk devices and future fully depleted multigate devices, parasitic contact resistivity must be reduced to ≈0.1 Ω · μm 2 on Si [1]. This is an enormous challenge for Si and poses an even larger problem if alternative channel substrates are considered. At present, silicide can provide a specific contact resistivity (ρ CO ) in the range of 3-10 Ω · μm 2 [2] but is limited by both the midgap Schottky barrier height (SBH) and the solid solubility of dopants in Si [3], [4]. Of these two limitations, adjusting the SBH is viewed as the best approach for contact resistivity reduction with silicide as doping levels are routinely at maximum solid solubility. While silicide is the contact material of choice in CMOS today, it will need to be replaced in the upcoming nodes due to Fermilevel pinning that limits the minimum SBH obtainable by silicide to ≈0.3 V from the conduction band edge (CBE) or valence band edge [3]. Additionally, silicide cannot be formed on alternative channel (III-V or other) substrates, and alloys of III-V or other semiconductors with transition metals do not achieve the robust cluster of physical and electrical properties that have made silicide so popular [5], [6]. In choosing a contact technology for future nodes, one must consider simultaneously the ultimate achievable contact resistivity, contact geometry, substrate material, and junction requirements. With the approach of 3-D and/or nonplanar devices, a conformal orientationindependent contact process is desired. Additionally, since the substrate material for future nodes is unclear at present, it is desirable to have a low-resistance contact methodology that is widely applicable to many semiconductors. Finally, given the extremely shallow junctions that will be employed in future nodes, it is the key to have a contact methodology that does not consume substrate material and maintains the nanometerscale junct...

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“…High-stress silicon nitride (SiN) liner stressor or contact etch stop layer has been adopted in the manufacturing of integrated circuits based on planar transistors. In FinFETs, significant I Dsat enhancement can also be achieved using the SiN liner stressor [8]- [12]. In p-channel FinFETs (p-FinFETs), diamond-like carbon (DLC) liner stressor has been demonstrated for strain engineering [13], [16].…”

Section: Introductionmentioning

confidence: 99%

Phase Change Liner Stressor for Strain Engineering of P-Channel FinFETs

Ding

Cheng

Koh

et al. 2013

IEEE Trans. Electron Devices

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A novel Ge 2 Sb 2 Te 5 (GST) liner stressor for enhancing the drive current in p-channel FinFETs (p-FinFETs) is demonstrated. When amorphous GST changes phase to crystalline GST (c-GST), the GST material contracts. This phenomenon is exploited for strain engineering of p-FinFETs. A GST liner stressor wrapping a p-FinFET can be shrunk or contracted to generate very high channel stress for drive current enhancement. Saturation drain current enhancement of ∼80% and linear drain current enhancement of ∼110% are observed for FinFETs with c-GST liner stressor over the control or unstrained FinFETs. The drain current enhancement is higher for 0°rotated FinFETs as compared with that of the FinFETs with 45°rotation, due to the orientation-dependent piezoresistance coefficients. The drain current enhancement increases with decreasing gate length. GST liner stressor could be a strain engineering option in sub-20-nm technology nodes. Index Terms-FinFET, Ge 2 Sb 2 Te 5 (GST), multigate FET, phase change, strain. Yinjie Ding (S'11) received the B.Eng. (Hons.) degree in electrical engineering from the National University of Singapore, Singapore, in 2009, where he is currently pursuing the Ph.D. degree in electrical engineering.He is working on strain engineering for advanced transistors.Ran Cheng (S'11) received the B.Eng. degree in electrical engineering from the National University of Singapore (NUS), Singapore, in 2009. She is currently pursuing the Ph.D. degree at NUS. Shao-Ming Koh (S'07) received the B.Eng. (Hons.) and Ph.D. degrees from the National University of Singapore, Singapore.He is currently with GLOBALFOUNDRIES, Singapore.

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Strain engineering in nanoscale CMOS FinFETs and methods to optimize R<inf>S/D</inf>

Cited by 6 publications

References 4 publications

Lattice strain analysis of silicon fin field-effect transistor structures wrapped by Ge2Sb2Te5 liner stressor

Lattice strain analysis of silicon fin field-effect transistor structures wrapped by Ge2Sb2Te5 liner stressor

Contact Resistance Reduction to FinFET Source/Drain Using Novel Dielectric Dipole Schottky Barrier Height Modulation Method

Phase Change Liner Stressor for Strain Engineering of P-Channel FinFETs

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