Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs

Krasteva, Yana Esteves; Jimeno, Ana B.; Torre, Eduardo de la; Riesgo, Teresa

doi:10.1109/rsp.2005.45

Cited by 31 publications

(9 citation statements)

References 11 publications

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“…A functional unit relocation method is presented in [64]; the process used relies on altering partial bit-stream structure (primarily the Frame Address Register (FAR)) to target different regions of the device; the proposed method is aimed at columnar devices such as the Virtex II. A second relocation method based on bit-stream manipulation is presented in [65]; this method allows functional unit relocation in tile-based FPGAs such as the Virtex 4 family of devices.…”

Section: Free Functional Unit Placement and Relocationmentioning

confidence: 99%

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Dumitriu¹

2023

Preprint

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A number of modern digital processing systems implement complex multi-mode applications with high performance requirements and strict operating constraints; examples include video processing and telecommunication applications. A number of these systems use increasingly large FPGAs as the implementation medium, due to reduced development costs. The combination of increases in FPGA capacity and system complexity has lead to a non-linear increase in system implementation effort. If left unchecked, implementation effort for such systems will reach the point where it becomes a design and development bottleneck. At the same time, the reduction in transistor size used to manufacture these devices can lead to increased device fault rates. To address these two problems, the Multi-mode Adaptive Collaborative Reconfigurable self-Organized System (MACROS) Framework and design methodology is proposed and described in this work. The MACROS Framework other the ability for run-time architecture adaptation by integrating FPGA configuration into regular operation. The MACROS Framework allows for run-time generation of Application-Specific Processors (ASPs) through the deployment, assembly and integration of pre-built functional units; the framework further allows the relocation of functional units without affecting system functionality. The use of functional units as building blocks allows the system to be implemented on a piece-by-piece basis, which reduces the complexity of mapping, placement and routing tasks; the ability to relocate functional units allows fault mitigation by avoiding faulty regions in a device. The proposed framework has been used to implement multiple video processing systems which were used as verification and testing instruments. The MACROS framework was found to successfully support run-time architecture adaptation in the form of functional unit deployment and relocation in high performance systems. For large systems (more than 100 functional units), the MACROS Framework implementation effort, measured as time cost, was found to be one third that of a traditional (monolithic) system; more importantly, in MACRO Systems this time cost was found to increase linearly with system complexity (the number of functional units). When considering fault mitigation capabilities, the resource overhead associated with the MACROS Framework was found to be up to 85 % smaller than a traditional Triple Module Redundancy (TMR) solution.

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Section: Free Functional Unit Placement and Relocationmentioning

confidence: 99%

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Dumitriu¹

2023

Preprint

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“…Furthermore, communication channels side BM-LUTs input and outputs have been interconnected and routed with the Xilinx ISE PAR tool using only the area reserved for communication channels allocation. This approach, different from the one presented in [17] permits to reduce the communication infrastructure design time, but increases amount of needed resources (LUTs) and the required routing control. The selected mapping of the NoC based SoC, called Dynamic The ideal mapping of a RN is to assign one slot to each RN element.…”

Section: B 2d Based Va Model -Drnocmentioning

confidence: 99%

Virtual Architectures for partial runtime reconfigurable systems. Application to Network on Chip based SoC emulation

Krasteva

Torre

Riesgo

2008

2008 34th Annual Conference of IEEE Industrial Electronics

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Abstract-The paper presents a method for designing Virtual Architectures (VAs) for partial runtime reconfigurable systems (pRTRs). The presented method permits to create flexible pRTRs. Such pRTR system is used as a core for a Network on Chip based SoC emulation. The main advantage of the emulation framework is that it permits fast emulation and design space exploration. The paper includes a brief description of all the building elements of the emulation framework and a use case that demonstrates the advantages of the designed pRTRs.

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“…Consequently, buses are good candidates for integrating also partially reconfigurable modules into a system at runtime. Most work done in this field is based on older Xilinx Virtex FPGA architectures that provide wires spanning over the complete horizontal device width and that can be used to build buses with tristate drivers [8,6,4,1,7]. However, tristate buses come along with some place and route restrictions and require timing parameters that must be met to turn buffers on-and-off.…”

Section: Buses For Reconfigurable Systemsmentioning

confidence: 99%

Efficient Reconfigurable On-Chip Buses for FPGAs

Koch

Haubelt

Teich

2008

2008 16th International Symposium on Field-Programmable Custom Computing Machines

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This paper presents techniques for generating on-chip buses suitable for dynamically integrating hardware modules into an FPGA-based SoC by partial reconfiguration. The buses permit direct connections of master and slave modules to the bus in combination with a flexible fine-grained module placement and with minimized latency and area overheads.A test system will demonstrate a transfer rate of 800 MB/s while providing an extreme high placement flexibility.

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Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs

Cited by 31 publications

References 11 publications

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Virtual Architectures for partial runtime reconfigurable systems. Application to Network on Chip based SoC emulation

Efficient Reconfigurable On-Chip Buses for FPGAs

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