Efficient Reconfigurable On-Chip Buses for FPGAs

Koch, Dirk; Haubelt, Christian; Teich, Jüergen

doi:10.1109/fccm.2008.33

Cited by 25 publications

(10 citation statements)

References 9 publications

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“…Solutions can be classified into three basic principles: on-chip buses are the most common way of linking together communicating modules. For example, [2] and [3] present on-chip buses for flexible module placement. Hard macros implement the communication infrastructure within the FPGA fabric.…”

Section: Related Workmentioning

confidence: 99%

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Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures

Wildermann

Angermeier

Sibirko

et al. 2012

International Journal of Reconfigurable Computing

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By means of partial reconfiguration, parts of the hardware can be dynamically exchanged at runtime. This allows that streaming application running in different modes of the systems can share resources. In this paper, we discuss the architectural issues to design such reconfigurable systems. For being able to reduce reconfiguration time, this paper furthermore proposes a novel algorithm to aggregate several streaming applications into a single representation, called merge graph. The paper also proposes an algorithm to place streaming application at runtime which not only considers the placement and communication constraints, but also allows to place merge tasks. In a case study, we implement the proposed algorithm as runtime support on an FPGA-based system on chip. Furthermore, experiments show that reconfiguration time can be considerably reduced by applying our approach.

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Section: Related Workmentioning

confidence: 99%

“…by partial reconfiguration. Sophisticated techniques [2,3] are provided as FPGA macros which allow partial reconfiguration at runtime, even during bus transactions. Such buses permit connections between modules, including the communication to and from components of the static part of the system.…”

Section: (D)mentioning

confidence: 99%

Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures

Wildermann

Angermeier

Sibirko

et al. 2012

International Journal of Reconfigurable Computing

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“…Our experimental board has a crossbar device that routes I/O signals dynamically from the periphery to the current position of the partial module [2], [3], [4].…”

Section: Challengesmentioning

confidence: 99%

Virtual area management: Multitasking on dynamically partially reconfigurable devices

Angermeier

Fekete

Kamphans

et al. 2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum (IPDPSW)

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Every year the computing resources available on dynamically partially reconfigurable devices increase enormously. In the near future, we expect many applications to run on a single reconfigurable device. In this paper, we present a concept for multitasking on dynamically partially reconfigurable systems called virtual area management. We explain its advantages, show its challenges, and discuss possible solutions. Furthermore, we investigate one problem in more detail: Packing modules with time-varying resource requests. This problem from the reconfigurable computing field results in a completely new optimization problem not tackled before. ILP-based and heuristic approaches are compared in an experimental study and the drawbacks and benefits discussed.

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“…The ReCoBus architecture [12] was developed to provide a sophisticated communication infrastructure for enabling a new dimension in modular FPGA design. The goal of the ReCoBus approach is to link together configuration bitstreams or completely routed netlists based on a predefined communication architecture.…”

Section: The Recobus Architecturementioning

confidence: 99%

A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs

Koch

Beckhoff

Teich

2009

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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In this paper, we present and analyze a sophisticated communication architecture that allows to integrate many different modules into a system by FPGA reconfiguration at runtime. Furthermore, we examine how this architecture can be implemented on low-cost Spartan-3 devices. It will be demonstrated that modules can be exchanged in a system without disturbing the communication architecture. The paper points out, that the capabilities of Spartan-3 FPGAs are sufficient to build complex reconfigurable systems.

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Efficient Reconfigurable On-Chip Buses for FPGAs

Cited by 25 publications

References 9 publications

Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures

Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures

Virtual area management: Multitasking on dynamically partially reconfigurable devices

A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs

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