A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs

Koch, Dirk; Beckhoff, Christian; Teich, Jüergen

doi:10.1145/1508128.1508170

Cited by 28 publications

(6 citation statements)

References 16 publications

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“…One approach is to utilize reconfigurable FPGA platform and integrate acceleration engines, such as Chimaera [4], Garp [5] and OneChip [6]. Moreover, there are several recent general FPGA research platforms, such as RAMP [7], MOLEN [8], Accelerator [9], RAMPSoC [10], ReMAP [11], ReconOS [12], Hthreads [13] and RecoBus [14]. These studies focus on providing reconfigurable FPGA based environments and related tools which can be utilized to construct application specific MPSoC.…”

Section: Related Workmentioning

confidence: 99%

Static or Dynamic: Trade-Offs for Task Dependency Analysis for Heterogeneous MPSoC

Guo

Wang

Zhou

et al. 2013

2013 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications

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Out-of-order execution scheme is one of the most promising technologies for task level parallelization in MPSoC design paradigms. However, it still poses a significant challenge to efficiently analyze the inter-task dependencies. This paper applies a traditional instruction level Scoreboarding algorithm at the task level in two forms: dynamic and static. A heterogeneous MPSoC prototype has been developed on FPGA with state-of-the-art dynamic partial reconfigurable technologies. The leverage between static and dynamic scheduling using task dependency analysis is obtained. Experimental results demonstrated a trade-off for the two modalities.

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Section: Related Workmentioning

confidence: 99%

Static or Dynamic: Trade-Offs for Task Dependency Analysis for Heterogeneous MPSoC

Guo

Wang

Zhou

et al. 2013

2013 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications

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“…Current state-of-the-art mature literatures includes following research projects: RAMP [4], MOLEN [5], Accelerator [6], RAMPSoC [7], ReMAP [8], ReconOS [9], Hthreads [10] and RecoBus [11]. However, the high level programming to circuits problem has not been completely figured out, which drives programmers to acquire full knowledge of the system to handle the tasks distribution manually.…”

Section: Related Work and Review Of Soamentioning

confidence: 99%

CaaS: Core as a service realizing hardware sercices on reconfigurable MPSoCS

Wang

Zhang

et al. 2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

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Service-oriented architecture (SOA) has been proved as an efficient way for high level programming paradigms. This paper realizes services into reconfigurable MPSoC to organize CaaS: a core as a service framework, which implements hardware services on state-of-the-art reconfigurable multi-processor system-on-chip (MPSoC) platform for high level parallelization. The integration of SOA concepts can provide structural programming models to ease the burden of high level programming. For demonstration, a prototype with JPEG application has been built on an FPGA, regarding embedded processors and IP cores as computing servants. The experimental results demonstrate the CaaS can achieve high flexibility with dynamic reconfigurable techniques.

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“…We modeled our experimental platform along the lines of ReCoBus [10] which supports complex run-time reconfiguration. The ReCoBus's reconfiguration regions are organized in terms of reconfigurable slots that are 6 CLB columns in size.…”

Section: A Experimental Setupmentioning

confidence: 99%

Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based Systems

Sim

Wong

Walla

et al. 2010

2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-One of the major impediments to deploying partially run-time reconfigurable FPGAs as hardware accelerators is the time overhead involved in loading the hardware modules. While configuration prefetching is an effective method that can be employed to reduce this overhead, mispredicted prefetches may worsen the situation by increasing the number of reconfigurations needed. In this paper, we present a static algorithm for configuration prefetching in partially reconfigurable FPGAs that minimizes the reconfiguration overhead. By making use of profiling, the interprocedural control flow graph, and the placement information of hardware modules, our algorithm predicts hardware execution and tries to prefetch hardware modules as early as possible while minimizing the risk of mis-predictions. Our experiments show that our algorithm performs significantly better than current-state-ofthe-art prefetching algorthms for control-bound applications.

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A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs

Cited by 28 publications

References 16 publications

Static or Dynamic: Trade-Offs for Task Dependency Analysis for Heterogeneous MPSoC

Static or Dynamic: Trade-Offs for Task Dependency Analysis for Heterogeneous MPSoC

CaaS: Core as a service realizing hardware sercices on reconfigurable MPSoCS

Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based Systems

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