STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems

Kestor, Gokcen; Gioiosa, Roberto; Harris, Tim; Unsal, Osman S.; Cristal, Adrián; Hur, Ibrahim; Valero, Mateo

doi:10.1109/pact.2011.54

Cited by 10 publications

(16 citation statements)

References 19 publications

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“…Under these hypothesis, devoting hardware threads to perform runtime operations rather than main computation may provide higher performance than using all available hardware resources to run application threads. STM 2 , in particular, provides significant speedups over canonical STM systems (between 1.8x and 5.2x on average) [17] for applications that spend a considerable amount of time performing transactions. However, similarly to other assisted execution systems, STM 2 may not fully utilize the processor's resources for some cases.…”

Section: Static Fine-grained Resource Partitioningmentioning

confidence: 99%

“…STM systems, however, usually suffer from high overhead, which makes them good candidates for assisted execution models. As a test case, we apply fine-grained hardware resource partitioning to STM 2 (Software Transactional Memory for Simultaneous Multithreading processors), an assisted execution STM system [17]. With STM 2 , transactional operations are divided between application and auxiliary threads: application threads optimistically perform computation, while time-consuming TM management operations, such as read-set validation, are handled by auxiliary threads.…”

Section: Introductionmentioning

confidence: 99%

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Enhancing the performance of assisted execution runtime systems through hardware/software techniques

Kestor

Gioiosa

Unsal

et al. 2012

Proceedings of the 26th ACM International Conference on Supercomputing

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To meet the expected performance, future exascale systems will require programmers to increase the level of parallelism of their applications. Novel programming models simplify parallel programming at the cost of increasing runtime overheard. Assisted execution models have the potential of reducing this overhead but they generally also reduce processor utilization.We propose an integrated hardware/software solution that automatically partition hardware resources between application and auxiliary threads. Each system level performs well-defined tasks efficiently: 1) the runtime system is enriched with a mechanism that automatically detects computing power requirements of running threads and drives the hardware actuators; 2) the hardware enforces dynamic resource partitioning; 3) the operating system provides an efficient interface between the runtime system and the hardware resource allocation mechanism. As a test case, we apply this adaptive approach to STM 2 , an software transactional memory system that implements the assisted execution model.We evaluate the proposed adaptive solution on an IBM POWER7 system using Eigenbench and STAMP benchmark suite. Results show that our approach performs equal or better than the original STM 2 and achieves up to 65% and 86% performance improvement for Eigenbench and STAMP applications, respectively.

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Section: Static Fine-grained Resource Partitioningmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Enhancing the performance of assisted execution runtime systems through hardware/software techniques

Kestor

Gioiosa

Unsal

et al. 2012

Proceedings of the 26th ACM International Conference on Supercomputing

Self Cite

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“…Concurrently with each application thread, a sibling thread in the style of [5] performs race detection using the Fasttrack algorithm [4]. This approach to parallelized runtime verification minimizes application slowdown.…”

Section: Introductionmentioning

confidence: 99%

“…With compiler support available for TM hardware, our approach will immediately enjoy the benefit of improved performance due to TM hardware. STM 2 [5] is a novel, multi-threaded STM design, where each application thread has a dedicated auxiliary ("sibling") thread performing STM operations such as validation of read-sets, bookkeeping and conflict detection. The communication between application and auxiliary thread is provided by a communication channel and atomic status variables.…”

Section: Introductionmentioning

confidence: 99%

PaRV: Parallelizing Runtime Detection and Prevention of Concurrency Errors

Kuru

Matar

Cristal

et al. 2013

Runtime Verification

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Abstract. We present the PaRV tool for runtime detection of and recovery from data races in multi-threaded C and C++ programs. PaRV uses transactional memory technology for parallelizing runtime verification and for buffering write accesses during race checking. Application threads are slowed down only due to instrumentation, but not due to the computation performed by runtime verification algorithms since the latter are run concurrently on different threads. Buffering writes allows us to recover from races and to safeguard against later ones.

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“…Recent work by Casper et al [3] and Kestor et al [20] suggests that moving validation off of the critical path and performing it out-of-band -in parallel with the "real work" of the transaction-can result in performance improvements of 1.7× and 1.8×-5.2× respectively. Naive out-of-band validation, however, allows inconsistent speculative transactions ("zombies") to execute erroneous operations that result in visible violations of the semantics of the source programming language.…”

Section: Introductionmentioning

confidence: 99%

Sandboxing transactional memory

Dalessandro

Scott

2012

Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques

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Correct transactional memory systems (TMs) must address the possibility that a speculative transaction may read mutually inconsistent values from memory and then perform an operation that violates the underlying language semantics. TMs for managed languages can leverage type safety, just-intime compilation, and fully monitored exceptions to sandbox transactions, isolating the rest of the system from damaging effects of inconsistent speculation. In contrast, TMs for unmanaged languages that lack these properties typically avoid erroneous behavior by validating a transaction's view of memory incrementally after each read operation.Recent results suggest that performing validation out-ofband can increase performance by factors of 1.7× to 5.2× over incremental validation, but allowing a transaction's main computation to progress in parallel with validation introduces periods in which inconsistent speculative execution may violate language semantics. Without sandboxing-which some authors have suggested is not possible in unmanaged languages-programmers must manually annotate transactions with validation barriers whenever inconsistency might lead to semantic violations, an untenable task.In this work we demonstrate that sandboxing for out-ofband validation is, in fact, possible in unmanaged languages. Our implementation integrates signal interposition, periodic validation, and a mix of static and dynamic instrumentation into a system comprising the LLVM-based Dresden TM compiler and the RSTM runtime. We show that these mechanisms introduce negligible overhead, thus extending the results of out-of-band validation to POSIX programs without requiring manual annotation. Furthermore, we establish sandboxing as a technique that can complement, or replace, incremental validation in any TM that keep speculatively written values in a private buffer.

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STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems

Cited by 10 publications

References 19 publications

Enhancing the performance of assisted execution runtime systems through hardware/software techniques

Enhancing the performance of assisted execution runtime systems through hardware/software techniques

PaRV: Parallelizing Runtime Detection and Prevention of Concurrency Errors

Sandboxing transactional memory

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