Steamroller Module and Adaptive Clocking System in 28 nm CMOS

Wilcox, Kathryn; Cole, Robert; Fair, Harry R.; Gillespie, Kevin; Grenat, Aaron; Henrion, Carson; Jotwani, Ravi; Kosonocky, Stephen; Munger, Benjamin; Naffziger, Samuel; Orefice, Robert S.; Pant, Sanjay; Priore, Donald A.; Rachala, Ravinder; White, Jonathan

doi:10.1109/jssc.2014.2357428

Cited by 34 publications

(11 citation statements)

References 7 publications

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“…Two major design approaches have been proposed to address the issues with such large timing margins [2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26].…”

Section: Introductionmentioning

confidence: 99%

Low-overhead, one-cycle timing-error detection and correction technique for flip-flop based pipelines

Koo

Park

Kim

et al. 2019

IEICE Electron. Express

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We propose a low-overhead, one-cycle timing-error detection and correction (EDAC) technique for flip-flop based pipelines. In order to prevent data collision during local clock gating for rapid error correction, the proposed technique performs clock gating of the master and the slave latches inside the flip-flops independently. Unlike previous flip-flop based one-cycle EDAC techniques, the independent clock gating in the proposed technique enables selective replacement of EDAC flip-flops, thereby reducing the area and power consumption overhead. Our experiments using a 3-stage pipeline consisting of 8-bit multipliers showed that the proposed technique improved the area and power consumption by 66% and 88%, respectively, compared to the state-of-the-art flip-flop based EDAC technique while showing a comparable area and power consumption with the two-phase latch based EDAC technique. A 32-bit, 5-stage MIPS microprocessor data path testchip based on the proposed technique was implemented in a 65 nm CMOS technology. With the proposed onecycle EDAC technique, the silicon measurement results from 31 dies showed 24.3% higher throughput and 8.7% less energy consumption beyond the point of the first failure (PoFF).

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“…Two major design approaches have been proposed to address the issues with such large timing margins [2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26].…”

Section: Introductionmentioning

confidence: 99%

Low-overhead, one-cycle timing-error detection and correction technique for flip-flop based pipelines

Koo

Park

Kim

et al. 2019

IEICE Electron. Express

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“…Conventionally, the decoupling capacitors are widely used for resonant power supply noise reduction, however, these decaps require large additional silicon area. In order to reduce this penalty, some other remedies are researched and proposed, such as adaptive clocking technologies [4]- [7]. Another technology to realize resonant power supply noise reduction with strict constraints of both the silicon area and performance in high frequency noise is an active charge injection.…”

Section: Introductionmentioning

confidence: 99%

Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise

Kano

Nakura

Asada

2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

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This paper proposes an analysis of the active charge injection for a resonant power supply noise by controlling the number of canceling capacitors so that the core supply voltage does not become lower than the voltage at the beginning of the canceling charge injection. Based on this analysis, we propose a circuit that injects adequate amount of charge in accordance with the injection time and the amount of the voltage drop whose code comes from an on-chip voltage drop detector. The proposed circuit is composed of a voltage drop detector, a finite state machine (FSM) that controls the injection and canceling capacitor circuit. The injection controller FSM enables the robust operation against the variation of the current consumed in the core circuit. The post-layout simulation indicates that our proposed circuit reduces the resonant power supply noise by about 30%, and also reduce 71% silicon area compared to the area of passive decoupling capacitors for the same amount of the noise reduction.

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“…In [42], the adaptive clocking system contains three PLLs running at independent frequencies with a multiplexer to switch between them using dynamic algorithms. The adaptive clocking design in [43] consists of a delay lock loop-based voltage droop detector and a digital frequency synthesizer that slows the clock as soon as a droop is detected. In the Razor-based 32-bit ARM processor [44], an adaptive controller tunes the operating frequency in response to timing error rates to contribute to the system energy savings.…”

Section: High-performance Processorsmentioning

confidence: 99%

“…However, an adaptive clock tracks supply noise by scaling the operational frequency in response to noise events and potentially attain a higher average system frequency. Adaptive clocking in [43] reduced the operational voltage for a given frequency by 3-6% and thereby, an increase of core power efficiency from 7-19%. An adaptive PLL demonstrated in [46] achieves up to a 15.6% improvement in maximum processor frequency or a 9.8% reduced…”

Section: High-performance Processorsmentioning

confidence: 99%

“…A traditional adaptive clock source scheme can dramatically reduce voltage guard-band or margin and guarantee failure-free operation in the presence of power supply noise. For instance, the operational voltage was reduced by 3-6% with the adaptive clocking scheme in [43]. However, certain local effects of power supply noise cannot be compensated by this scheme.…”

Section: Approachmentioning

confidence: 99%

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Modeling and Design for Low Power and Variation Tolerance in Integrated Circuits

Kamakshi¹

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Modern integrated circuits ranging from ultra-low power internet-of-things devices to high-performance processors cater to a wide spectrum of applications and notably aid in revolutionizing human lifestyle. For instance, wearable technology is a ubiquitous internetof-things application that has made great strides in the healthcare and fitness domain. High-performance chips such as graphics processing units enable an efficient computation platform for both graphics and non-graphics applications. However, along with the capability to support an ever-increasing scope of applications, these integrated circuits are also faced with a multitude of design challenges. In this work, we aim to address two such challenges: power consumption and tolerance to circuit or environmental variations, in two key markets of the semiconductor industry, namely internet-of-things and high-performance computing. Low-power operation is a crucial requirement in modern integrated circuits design. In self or battery-powered internet-of-things devices that are required to have a long lifetime, ultra-low power circuit design is of utmost importance due to limited battery capacities and efficiency of current energy harvesting technology. Ultra-low power operation increases the prospects of their sustainable or even perpetual operation. In the high-performance domain, advanced technologies and faster clock frequencies have led to an increase in static and dynamic power consumption. Low power consumption is necessary for longer battery lifetimes in portable devices like tablets and laptops. It is also crucial to reduce the thermal hot-spots and the need for heat-sinks in such processors. In this work, we investigate low power circuits and systems especially targeting the self/battery-powered applications.

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Steamroller Module and Adaptive Clocking System in 28 nm CMOS

Cited by 34 publications

References 7 publications

Low-overhead, one-cycle timing-error detection and correction technique for flip-flop based pipelines

Low-overhead, one-cycle timing-error detection and correction technique for flip-flop based pipelines

Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise

Modeling and Design for Low Power and Variation Tolerance in Integrated Circuits

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