Statistical timing analysis for intra-die process variations with spatial correlations

Agarwal, Aseem; Blaauw, David; Zolotov, Vladimir

doi:10.1109/iccad.2003.159781

Cited by 340 publications

(235 citation statements)

References 19 publications

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“…The spatial correlations is modelled by using a grid model for the circuit as shown in Figure One other model to consider spatial correlation is the Quadtree model as in the work by [1]. The Quadtree model also partition the chip area into square grids.…”

Section: Statistical Timing Analysismentioning

confidence: 99%

Timing Verification for Adaptive Integrated Circuits

Kumar¹,

Li²,

Shen³

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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An adaptive circuit can perform built-in self-detection of timing variations and accordingly adjust itself to avoid timing violations. Compared with conventional over-design approach, adaptive circuit design is conceptually advantageous in terms of power-efficiency. Although the advantage has been witnessed in numerous previous works including test chips, adaptive design is far from being widely used in practice.A key reason is the lack of corresponding timing verification support. We developed new timing analysis techniques to fill this void. A main challenge is the large runtime complexity due to numerous adaptivity configurations. We propose several pruning and reduction techniques and apply them in conjunction with statistical static timing analysis (SSTA). The proposed method is validated on benchmark circuits including the recent ISPD'13 suite, which has circuit as large as 150K gates. The results show that our method can achieve orders of magnitude speed-up over Monte Carlo simulation with about the same accuracy. It is also several times faster than an exhaustive application of SSTA.

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Section: Statistical Timing Analysismentioning

confidence: 99%

Timing Verification for Adaptive Integrated Circuits

Kumar¹,

Li²,

Shen³

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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“…Since we assume that Lg or Wg are correlated, a possible approach to model intra-die spatial correlations is to use the approach presented in [1]. The main idea is to divide the circuit into a number of regions using a multi-level quad-tree partition.…”

Section: Process Parameter Variation-aware Modelmentioning

confidence: 99%

Process variability-aware transient fault modeling and analysis

Chopra

Zhuo

Blaauw

et al. 2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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-Due to reduction in device feature size and supply voltage, the sensitivity of digital systems to transient faults is increasing dramatically. As technology scales further, the increase in transistor integration capacity also leads to the increase in process and environmental variations. Despite these difficulties, it is expected that systems remain reliable while delivering the required performance. Reliability and variability are emerging as new design challenges, thus pointing to the importance of modeling and analysis of transient faults and variation sources for the purpose of guiding the design process. This work presents a symbolic approach to modeling the effect of transient faults in digital circuits in the presence of variability due to process manufacturing. The results show that using a nominal case and not including variability effects, can underestimate the SER by 5% for the 50% yield point and by 10% for the 90% yield point.

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“…As will be explained in Section 4, we use this fact to incorporate the spatial correlations between the random parameter variations. To generate the uncertainty ellipsoid region, it is not required to make any assumptions about the distributions of the W and L. The only inputs needed to generate the P matrix are the standard deviations of the components of X, which can be empirically calculated [15], and correlation factors between the components of X, which can be derived from a spatial correlation model such as the ones used in [13] and [14].…”

Section: Uncertainty Ellipsoidmentioning

confidence: 99%

“…We use the grid based spatial correlation model of [13] and [14] to incorporate the intra-die correlations between the device W and L variations. For a random vector X representing the variations in W and L and its corresponding covariance matrix P , the entry Pij = σiσj ρij denotes the covariance between components i and j of X, where σ is the standard deviation of each random variable and ρij is the correlation factor between the random variables i and j.…”

Section: Incorporating Spatial Correlationsmentioning

confidence: 99%

“…Our robust gate sizing scheme is a type of worst-case design method, but by incorporating spatial correlations in the design procedure, we reduce some pessimism in the design. Spatial intra-die correlations between the parameter variations are incorporated in the optimization scheme by using a grid-based spatial correlation model used in [13] and [14]. We focus on the intradie variations in L and W parameters; however, the method can be easily modified to include inter-die variations.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Robust gate sizing by geometric programming

Singh¹,

Nookala²,

Luo³

et al. 2005

Proceedings. 42nd Design Automation Conference, 2005.

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We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporate uncertainty in the transistor widths and effective channel lengths due to the process variations. An uncertainty ellipsoid method is used to model the random parameter variations. Spatial correlations of intra-die width and channel length variations are incorporated in the optimization procedure. The resulting optimization problem is relaxed to be a Geometric Program and is efficiently solved using convex optimization tools. The effectiveness of our robust gate sizing scheme is demonstrated by applying the optimization on the ISCAS '85 benchmark circuits and testing the optimized circuits by performing Monte Carlo simulations to model the process variations. By varying the size of the uncertainty ellipsoids, a trade-off between area and robustness is explored. Experimental results show that the timing yield of the robustly optimized circuits improves manifold over the traditional deterministically sized circuits. As compared to the worst-case design, the robust gate sizing solution having the same area, has fewer timing violations.

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Statistical timing analysis for intra-die process variations with spatial correlations

Abstract: Abstract

Cited by 340 publications

References 19 publications

Timing Verification for Adaptive Integrated Circuits

Timing Verification for Adaptive Integrated Circuits

Process variability-aware transient fault modeling and analysis

Robust gate sizing by geometric programming

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