Statistical techniques for the computer-aided optimization of analog integrated circuit

Abstract

A CAD tool capable of performing statistical circuit simulation, design, and optimization is described. The core of this tool is a general, CAD-compatible, statistical model which accounts for the effect of device area, transistor bias, and circuit layout on the variation of MOS integrated circuits. The statistical model has been incorporated into an object-oriented circuit simulator, APLAC, which has sufficient flexibility to allow optimization loops within a simulation input deck. The optimization of a two-stage operational amplifier, including the optimization of the standard deviation of the offset voltage, is performed using both steepest descent and constrained optimization techniques as an illustration of this statistical CAD tool. In this example, it is shown that the transistors which cause variations in op-amp circuit performance can be identified and resized in an area-efficient manner to meet a prescribed parametric circuit yield.

Statistical Compact Modeling and Si Verification Methodology

“…If this is not possible or too costly, for example for circuit timing simulations, then the models should incorporate the variations in the physical parameters. At this step, the physical parameters, such as width and height, will likely be correlated, and hence necessary computational methods such as principal component analysis [9] or alternatives [10] should be implemented in order to reduce or eliminate the inaccuracies caused by correlation between parameters.…”

A Typical MOSFET Modeling Procedure for RF Analog Circuit Design

“…There are many papers such as [2][3][4][5] describing statistical modeling published in the last two decades. The paper [2] uses on-wafer process parametric test (E-test) [7] parameters for finding corner device specifications.…”

“…The paper [2] uses on-wafer process parametric test (E-test) [7] parameters for finding corner device specifications. The papers [3] and [4] focused on model parameter yields. The paper [5] developed new methods to define boundary models.…”

An application-level synthesis methodology for multidimensional embedded processing systems

“…Subsequent yield improvement techniques move the circuit parameters from an initial configuration toward a new point which maximizes some figure of merit (e.g., the distance from the point to the acceptability region border or its approximation [12]- [15]). Yield improvement is an optimization problem and is solved with linear programming techniques (see [18] for a review) or with gradient descent-based techniques [12]- [15], [19].…”