Statistical Compact Modeling and Si Verification Methodology

Abstract

As we scale down to sub-65nm technologies, transistors and interconnects no longer act as predictable elements, but start acting as statistical blocks due to static and dynamic variations. This invited talk first reviews some of the key variations that need to be considered for any statistical analysis. Also, details for implementing statistical models into compact modeling flow are discussed. Finally, the paper reviews one of the techniques used for generating and validating statistical models with the silicon data.

A Simulation Algorithm for Prediction of Random Variations in Digital Circuits

“…Aggressive scaling of device dimensions into ultra short channel regime leads to significant process and intrinsic parameter fluctuations [1][2][3]. These fluctuations have caused reliability issues which in turn results in a waste of both time and cost.…”