Statistical Simulation of Static Noise Margin Variability in Static Random Access Memory

Li, Yiming; Cheng, Hui-Wen; Han, Ming-Hung

doi:10.1109/tsm.2010.2056710

Cited by 20 publications

(9 citation statements)

References 28 publications

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“…Also, it should be noted that the FinFET based structures have higher read SNMs compared to those of the corresponding planar bulk structures. This is due to the better control of the short channel effect as mentioned previously as well as larger transconductance than that of the conventional bulk [14]. Another important parameter in the read state is the access time for which the read current is used as a metric [6].…”

Section: A Read Statementioning

confidence: 99%

Low power and robust 8T/10T subthreshold SRAM cells

Ebrahimi

Afzali-Kusha

2012

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD

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In this paper, we propose a novel 8T subthreshold SRAM cell for improving the writing "0" characteristics of the conventional 8T cell. In addition, a new 10T subthreshold SRAM cell based on FinFET structures which has a lower standby power is suggested. The characteristics of the proposed and conventional 8T and 10T structures in 32 nm planar bulk and FinFET technologies are compared. The results show that the 10T structures have better write characteristics thanks to the differential write and consume less static power while the 8T structures have higher read currents. Also, they reveal that FinFET based structures show better read and write characteristics while consuming less static power with less variation in the presence of process variations.

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Section: A Read Statementioning

confidence: 99%

Low power and robust 8T/10T subthreshold SRAM cells

Ebrahimi

Afzali-Kusha

2012

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD

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“…Owing to lack of well-established compact models for the 16-nm-gate CMOS devices, by using the coupled devicecircuit simulation technique, [3][4][5] the circuit level fluctuations are estimated for the CMOS inverter circuit, as shown in Fig. 1(c), where the flowchart of coupled device-circuit simulation is shown in Fig.…”

Section: Itf Simulation Proceduresmentioning

confidence: 99%

Random Interface-Traps-Induced Electrical Characteristic Fluctuation in 16-nm-Gate High-κ/Metal Gate Complementary Metal–Oxide–Semiconductor Device and Inverter Circuit

Cheng

2012

Jpn. J. Appl. Phys.

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Within the framework of the thermally activated process of the flux line or flux line bundles, and by time integration of the 1D equation of motion of the circulating current density J (ρ, t), which is suitable for thin superconducting films (R d, λ), we present numerical calculations of the current profiles, magnetization hysteresis loops and ac susceptibility χ n = χ n + iχ n for n = 1, 3 and 5 of a thin disc immersed in an axial time-dependent external magnetic field B a (t) = B dc + B ac cos(2πνt). Our calculated results are compared with those of the critical state model (CSM) and found to prove the approximate validity of the CSM below the irreversibility field. The differences between our computed results and those of the CSM are also discussed.

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“…Devices with high-κ/metal-gate (HKMG) [1][2] and strained technologies [3][4] are important not only for nowadays planar metal-oxide-semiconductor field effect transistor (MOSFET) devices but also for advanced bulk FinFET devices. Devices with HKMG stacks can reduce the gate leakage; and, the source/drain (S/D) epi growth will boost device performance; however, characteristic fluctuations resulting from process variation effects and random effects [5][6][7] complicate process development of the 16-nm devices. In addition, the presence of shrunk S/D dimension results in large S/D series resistance [8][9].…”

Section: Introductionmentioning

confidence: 99%

Source/Drain Series Resistance Extraction in HKMG Multifin Bulk FinFET Devices

2015

IEEE Trans. Semicond. Manufact.

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Effective extraction of source/drain (S/D) series resistances is a challenging task owing to poor epi-growth and non-uniform distribution of current density in S/D, critical limitation of restrictive design rule, ultra-thin contact film, and complicated 3D FinFET structure. In this paper, we report a test structure for measurement of linear and non-linear S/D series resistances. This technique enables us to evaluate each component of S/D series resistances resulting from the S/D contact, the S/D epi-growth fin, the S/D extension, and the channel gate, respectively. The S/D series resistance for fins on different layout location of the same diffusion is characterized and modeled by connection with a specified S/D contact on it. Furthermore, the S/D series resistance of each fin can be analytically calculated, respectively, by swapping the S/D bias condition. The proposed test structure and extraction technique provides a robust monitoring tool to diagnose a process weak point of the 16-nm multi-fin high-κ/metal gate bulk FinFET devices.

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Statistical Simulation of Static Noise Margin Variability in Static Random Access Memory

Cited by 20 publications

References 28 publications

Low power and robust 8T/10T subthreshold SRAM cells

Low power and robust 8T/10T subthreshold SRAM cells

Random Interface-Traps-Induced Electrical Characteristic Fluctuation in 16-nm-Gate High-κ/Metal Gate Complementary Metal–Oxide–Semiconductor Device and Inverter Circuit

Source/Drain Series Resistance Extraction in HKMG Multifin Bulk FinFET Devices

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