Source/Drain Series Resistance Extraction in HKMG Multifin Bulk FinFET Devices

Abstract

Effective extraction of source/drain (S/D) series resistances is a challenging task owing to poor epi-growth and non-uniform distribution of current density in S/D, critical limitation of restrictive design rule, ultra-thin contact film, and complicated 3D FinFET structure. In this paper, we report a test structure for measurement of linear and non-linear S/D series resistances. This technique enables us to evaluate each component of S/D series resistances resulting from the S/D contact, the S/D epi-growth fin, the S/D extension, and the channel gate, respectively. The S/D series resistance for fins on different layout location of the same diffusion is characterized and modeled by connection with a specified S/D contact on it. Furthermore, the S/D series resistance of each fin can be analytically calculated, respectively, by swapping the S/D bias condition. The proposed test structure and extraction technique provides a robust monitoring tool to diagnose a process weak point of the 16-nm multi-fin high-κ/metal gate bulk FinFET devices.

Multi-Channel Step FinFET With Spacer Engineering

“…Presently, researchers are demonstrating interest in constructing FinFET devices based on multiple channels or Fins, known as Multi-Fin FinFET. [12], [13] configuration is the updated FinFET device where multiple Fins are placed in between the source and drain regions. To the authors' best knowledge, the multi-channels step FinFET (M ch step FinFET) device structure is not explored yet.…”