Statistical Assessment of High-Performance Scaled Double-Gate Transistors from Monolayer WS₂

Abstract

Scaling of monolayer transition metal dichalcogenide (TMD) field-effect transistors (FETs) is an important step toward evaluating the application space of TMD materials. Although some work on ultrashort channel monolayer (ML) TMD FETs has been published, there exist no comprehensive studies that assess their performance in a statistically relevant manner, providing critical insights into the impact of the device geometry. Part of the reason for the absence of such a study is the substantial variability of TMD devices when processes are not carefully controlled. In this work, we show a statistical study of ultrashort channel double-gated ML WS2 FETs exhibiting excellent device performance and limited device-to-device variations. From a detailed analysis of cross-sectional scanning transmission electron microscopy (STEM) images and careful technology computer aided design (TCAD) simulations, we evaluated, in particular, an unexpected deterioration of the subthreshold characteristics for our shortest devices. Two potential candidates for the observed behavior were identified, i.e., buckling of the TMD on the substrate and loss of gate control due to the source geometry and the high-k dielectric between the metal gate and the metal source electrode.

Review—Extremely Thin Amorphous Indium Oxide Transistors

“…Shaded areas represent the most desirable regions of device operation for logic transistors. Data sources: indium oxide, [106,[110][111][112][113] ITO, [100,142,99] IGZO, [143][144][145][146]97] IWO, [102,135] ZnO, [147] MoS 2 , [148][149][150][151][152][153][154][155][156] WS 2 , [157][158][159][160] Te, [161] WSe 2 , [162] black phosphorus, [163][164][165] GaN, [166] InGaAs, [167] InAs, [168] Si. [116] conditions [110] with disadvantages in process maturity, geometry (planar versus fin), and device scaling (40 nm channel length versus the 4 nm-equivalent node).…”

Self-Aligned Top-Gate Structure in High-Performance 2D p-FETs via van der Waals Integration and Contact Spacer Doping

“…Furthermore, Sun et al reported that the use of a partially metal covered TG stack results in a more significant shortchannel effect due to the fringing field, in contrast to fully covered TG stack. 24 Figure 2d illustrates the band structure of our novel TG device with a fully metal covered hBN stack achieved through vdW transfer (L tg is approximately 500 nm). Using TG metal electrodes as an etching mask ensures well matching alignment between metal electrode and hBN dielectric, giving rise to effective TG control.…”

“…To address this limitation, the lateral junction devices are proposed by patterning the doping profile of the channel area, offering improved electrostatic controllability of oxidized WSe 2 FETs through the generation of a built-in potential. ,,,− Furthermore, using a top-gate (TG) to modulate the built-in potential can be an effective approach for achieving high-performance p-FETs. , However, achieving a narrow top-gate length ( L tg ) in the R&D environment is challenging when using conventional top-gate fabrication methods that employ oxygen plasma doping at the spacer area. Additionally, challenges are presented when 2D materials are employed as a channel, e.g., transfer of dielectric layer and additional lithographic patterning process to precisely positioning TG electrodes, which limit the yield of fabrication process contributing to realization of high-performance p-FETs and p-type metal-oxide-semiconductor (PMOS) inverter …”

“…Furthermore, Sun et al. reported that the use of a partially metal covered TG stack results in a more significant short-channel effect due to the fringing field, in contrast to fully covered TG stack …”

“…Additionally, challenges are presented when 2D materials are employed as a channel, e.g., transfer of dielectric layer and additional lithographic patterning process to precisely positioning TG electrodes, which limit the yield of fabrication process contributing to realization of high-performance p-FETs and p-type metal-oxide-semiconductor (PMOS) inverter. 24 In this study, we present a novel approach to achieve highperformance lateral p + −p−p + junction WSe 2 FETs with controlled L tg . Our method involves self-aligned TG stacks by van der Waals (vdW) integration, followed by oxygen plasma doping at contact and spacer regions of FETs.…”