Statistical Approach to Networks-on-Chip

Cohen, Itamar; Rottenstreich, Ori; Keslassy, Isaac

doi:10.1109/tc.2010.35

Cited by 9 publications

(4 citation statements)

References 42 publications

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“…They are sometimes referred as upper bound delay and lower bound bandwidth of flows. Historically, designers have focused on extracting the average delay and average bandwidth, and a large body of work to extract such parameters exists [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33]. Simulation and mathematical modeling are two different approaches to do so.…”

Section: Related Workmentioning

confidence: 99%

“…Therefore, they can be used within design tools, for example, to iterate in the NoC synthesis process to tailor NoC architectures for specific applications. Frequently used mathematical frameworks are queuing theory and statistical timing analysis [25], [26], [28], [31]. A node is modeled as a queuing system, which can be M=G=1; M=G=1=t; G=G=1, etc.…”

Section: Related Workmentioning

confidence: 99%

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Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Rahmati

Murali

Benini³

et al. 2013

IEEE Trans. Comput.

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Abstract-Real-time (RT) communication support is a critical requirement for many complex embedded applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper, we present novel methods to efficiently calculate worst case bandwidth and latency bounds for RT traffic streams on wormhole-switched NoCs with arbitrary topology. The proposed methods apply to best-effort NoC architectures, with no extra hardware dedicated to RT traffic support. By applying our methods to several realistic NoC designs, we show substantial improvements (more than 30 percent in bandwidth and 50 percent in latency, on average) in bound tightness with respect to existing approaches.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Rahmati

Murali

Benini³

et al. 2013

IEEE Trans. Comput.

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“…It is worth noting that traffic pattern usually gives average bandwidth that flows demand. However, according to [13], massages are often transferred in burst-mode, which requires higher bandwidth temporally, so link capacity with bandwidth slack is necessary. Our Algorith m can add an additional weight to v(i,j) to satisfy these situations.…”

Section: A Bandwidth-based Application-aware Routing Algorithm (Bamr)mentioning

confidence: 99%

Bandwidth-based Application-Aware Multipath Routing for NoCs

Ding¹,

Yang²,

Ren³

et al. 2015

Proceedings of the International Conference on Computer Information Systems and Industrial Applications

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Abstract--Most of routing algorithms for On-chip communication are neither application-aware nor routing packets using multiple paths. In addition, they hardly consider link bandwidth variation resulting from widely applied global asynchronous local synchronous (GALS ) mechanism. In this paper, we propose a bandwidth-based application-aware multipath routing (BAMR) algorithm to assign multiple routing paths by leveraging the knowledge of application and network bandwidth features. With the increase of number of flows resulting from the split of flows, we present a new method named dynamic-amount fixed-number (DAFN) flow control mechanism to avoid deadlock. We compare our algorithm with XY, YX, an d O1TURN with synthetic traffic patterns and traffic trace of parallel implementation of H.264. Experiments demonstrate that BAMR achieves higher throughput with decrease in latency. Furthermore, the proposed algorithm achieves better workload balance by distributing traffic over multiple paths.

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“…A system of benchmarks for NoCs, which covers a wide spectrum of NoC design aspects, from application modeling to performance evaluation, has been presented in [31]. A statistical approach to traffic modeling using traffic-load distribution plots that prevents overprovisioning for network link capacities is presented in [32]. A statistical physics-inspired approach to capture the capture the non-stationary traffic dynamics in multicore systems is presented in [103].…”

Section: State Of the Art In Network-on-chipmentioning

confidence: 99%

On-Chip Network-Enabled Many-Core Architectures for Computational Biology Applications

Majumder¹,

Pande²,

Kalyanaraman³

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Large-scale integration of multiple cores on a single chip is the current answer to the challenge of attaining higher computation throughput while restricting power consumption within acceptable limits. Network-on-Chip (NoC) is an emerging paradigm that can efficiently support integration of a massive number of cores on a chip by decoupling the on-chip computation and communication infrastructure, thereby overcoming scalability issues faced by conventional buses.Many scientific computing disciplines, such as computational biology, have seen a significant increase in the availability of parallel algorithms and highperformance computing (HPC) tools owing to high runtime complexities and/or the data-intensive nature underlying the computation. Software-only solutions are likely to be inadequate, creating the need for hardware accelerators. This dissertation explores the design and development of highly optimized NoC-based hardware accelerators for a particular class of biocomputing applications, viz. phylogeny reconstruction, which is important for evolutionary inferences in computational biology. This dissertation focuses on two computationally distinct phylogeny reconstruction approaches to demonstrate that NoC-based many-core platforms can deliver orders of magnitude reduction in time-to-solution, compared to v existing approaches. The Maximum Parsimony (MP) phylogeny reconstruction problem can be reduced to one of solving numerous instances of the classical Traveling Salesman Problem (TSP). 99% of the total software runtime is spent in computing TSP instances, whose solution typically involves an application of branch-and-bound runtime heuristics. This dissertation presents the design of many-core systems with core-level pipelined micro-parallel architecture and different interconnection topologies to achieve significant speedup and energy efficiency. In Maximum Likelihood (ML) phylogeny reconstruction, the improved quality of result comes at a higher computational cost, as this approach involves optimization over multi-dimensional real continuous space. We present NoCbased hardware accelerators that target function kernels contributing to a bulk of the runtime. These platforms combine novel ideas and approaches, such as space-filling Hilbert curves, parallelized core allocation schemes, and 3-D integration. We also explore the use of long-range on-chip wireless links on existing regular topologies to reduce network diameter, thereby reducing the average communication latency between cores. These platforms have the potential to serve a broader class of throughput-oriented HPC applications. viTable of Contents

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Statistical Approach to Networks-on-Chip

Cited by 9 publications

References 42 publications

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Bandwidth-based Application-Aware Multipath Routing for NoCs

On-Chip Network-Enabled Many-Core Architectures for Computational Biology Applications

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