Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs

Abstract

Statistical characteristics of intrinsic channel fully depleted (FD) SOI MOSFETs and conventional bulk MOSFETs are compared. It is experimentally shown that not only threshold voltage (Vth) variability but drain induced barrier lowering (DIBL) and current onset voltage (COV) variability is well suppressed in FD SOI MOSFETs. Moreover, time-dependent Vth change due to random telegraph noise (RTN) is also smaller in FD SOI MOSFETs. The mechanisms of these variability suppressions are discussed using three dimensional device simulation and it terms out that the absence of random dopant fluctuation (RDF) is responsible for the suppressed variability. These results strongly demonstrate the advantage of intrinsic channel MOSFETs where the channel does not include dopant atoms.

Inexact computing using probabilistic circuits

“…Since an FDSOI device is experimentally shown that process variability such as V th , DIBL, and current onset voltage (COV) is well suppressed compared to bulk CMOS, this can motivate us to apply our probabilistic approach with less effect from intrinsic variability of the device itself when performing statistical analysis. Moreover, time-dependent V th change due to random telegraph noise is also smaller in FDSOI MOSFETs [Hiramoto et al 2011], so using AWGN for the noise source can be more effective for FDSOI than for a bulk counterpart. Some important parameters used during the simulation are summarized in Table I.…”

Monte Carlo simulation of random dopant fluctuation in C–V characteristics using image charge model and adequately determined length scale

“…20) These fluctuations may be understandable if two transistors having different spatial distributions of dopant ions result in two different threshold voltages. In order to suppress the issues of RDF in device engineering, several methods have been proposed such as lightly doped epitaxial layers with δ-doped channels, 21) intrinsic-channel fully depleted SOI MOSFETs, 22) and so on. If the DD model is used in device simulation and the PN junction in device engineering, the length scale must be shorter than the mean distance in order to distinguish the spatial distribution of discrete dopant ions from the continuous concentration of dopant ions in the DD model.…”

Performance Fluctuations in 10-nm Trigate Metal–Oxide–Semiconductor Field-Effect Transistors: Impact of the Channel Geometry

“…To minimize fluctuations due to RDD, MOSFET concepts with undoped channels are suggested. [9][10][11] Among them, the trigate SOI MOSFET [12][13][14] is one of the most promising candidates for CMOS generations with gate lengths below 20 nm. Since the channel is undoped, the electrostatic integrity of a trigate MOSFET strongly depends on the body geometry, i.e., on the width w Si , height t Si , and length L G of the silicon body (Fig.…”