Static Timing Model Extraction for Combinational Circuits

Abstract

Abstract. For large circuits, static timing analysis (STA) needs to be performed in a hierarchical manner to achieve higher performance in arrival time propagation. In hierarchical STA, efficient and accurate timing models of sub-modules need to be created. We propose a timing model extraction method that significantly reduces the size of timing models without losing any accuracy by removing redundant timing information. Circuit components which do not contribute to the delay of any input to output pair are removed. The proposed method is deterministic. Compared to the original models, the numbers of edges and vertices of the resulting timing models are reduced by 84% and 85% on average, respectively, which are significantly more than the results achieved by other methods.

From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era

“…The methods in Refs. [26], [27], [28], [29] apply graph transformation operations to merge nodes and edges representing the timing information of the original circuit, leading to gray-box timing models because timing information inside the modules is exposed. For sequential circuits, Interface Logic Model (ILM) in Ref.…”

“…When process variations are considered, timing model extraction methods for combinational circuits and sequential circuits with flip-flops in Refs. [25], [26], [27], [28], [29] can be applied similarly, but with the maximum and sum computations replaced by the corresponding statistical versions. For sequential circuits with latches, the depth of transparency becomes statistical [31], [32].…”