Static Estimation of Execution Times for Hardware Accelerators in System-on-Chips

Abstract

Abstract-Early performance estimation of a System-on-Chip design is a key issue for a successful design methodology. One of the most important parameters is the run time of a function. Especially optimization techniques like hw/sw partitioning rely on those estimations. This paper presents a static analysis method in order to characterize a hardware acceleration unit regarding its run time. The performance of the presented method is shown on several examples from the embedded systems area and compared to results from high level synthesis.

Quipu

“…In this section, we summarize the main approaches in the field of hardware estimation. We investigate what part of a design they estimate, if they are dependent on a particular tool or platform, what hardware Other [Enzler et al 2000] Entire design Generic Area, Frequency DFG (RTL) [Lakshmi et al 2011] Entire design Xilinx Power FPGA netlist [Schumacher et al 2008] Entire design Xilinx Area, Delay, Power (V)HDL [Nayak et al 2002] Entire design MATCH Area (V)HDL [Brandolese et al 2004] Entire design SystemC Area SystemC [Bilavarn et al 2006] Entire design Design-Trotter Area HCDFG [Deng et al 2008] IP core specific TANOR Area, Power HLL (MATLAB) [Chuong et al 2009] Controller Trimaran Area, Delay HLL (C) LR/HLL(C) [So et al 2003] Loop nests DEFACTO Area HLL (C) [Holzer and Rupp 2005] Entire design SPARK Delay HLL (C) [Degryse et al 2008] Loop controller CLoogVHDL Area, Frequency HLL (C) [Kulkarni et al 2006] Entire design SA-C Area HLL (C) [Cilardo et al 2010] Entire design Generic a Area HLL (C) Quipu…”

“…Furthermore, although Nayak et al [2002], Brandolese et al [2004], Bilavarn et al [2006], Deng et al [2008], and Chuong et al [2009] targeted HLLs, they did not support ANSI-C. Therefore, in the following, we narrow our focus on several approaches that deal with both statistics and ANSI-C. Holzer and Rupp [2005] presented a custom model for execution time estimation based on the SPARK C-to-VHDL compiler [Gupta et al 2003]. They briefly mentioned SCMs, measures that characterize software descriptions, although they only use a critical path estimation scheme based on Control Flow Graphs (CFGs).…”

Design Space Exploration with Evolutionary Multi-Objective Optimisation

“…Execution time measured in cycles is based on the analysis of the depth of the DFG of one basic block [17]. Area measured in gates is estimated based on the number of required resources like ADD, SUB, MUL, or DIV and the number of control states.…”

Novel Genome Coding of Genetic Algorithms for the System Partitioning Problem

“…However, this modification does not change the character of the multi-objective optimisation problem. These values are usually obtained by high level synthesis [8] or estimation techniques like static code analysis [21] or profiling [22]. The plurality of implementation alternatives results from a variation of synthesis parameters, e.g.…”