Static energy reduction techniques for microprocessor caches

Hanson, Heather; Hrishikesh, M.S.; Agarwal, Vikas; Keckler, Stephen W.; Burger, Doug

doi:10.1109/iccd.2001.955040

Cited by 46 publications

(44 citation statements)

References 9 publications

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“…Turning these unused registers into a low-power state (drowsy state) the power consumption can be reduced to a minimum without data lost (Hanson et al, 2001).…”

Section: Background On Energy Reductionmentioning

confidence: 99%

A hardware mechanism to reduce the energy consumption of the register file of in-order architectures

Ayala¹,

López‐Vallejo²,

López-Barrio³

et al. 2008

IJES

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This paper introduces an efficient hardware approach to reduce the register file energy consumption by turning unused registers into a low power state. Bypassing the register fields of the fetch instruction to the decode stage allows the identification of registers required by the current instruction (instruction predecode) and allows the control logic to turn them back on. They are put into the low-power state after the instruction use. This technique achieves an 85% energy reduction with no performance penalty.Keywords: register file; in-order; power reduction; predecode; hardware approach.

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“…Turning these unused registers into a low-power state (drowsy state) the power consumption can be reduced to a minimum without data lost (Hanson et al, 2001).…”

Section: Background On Energy Reductionmentioning

confidence: 99%

A hardware mechanism to reduce the energy consumption of the register file of in-order architectures

Ayala¹,

López‐Vallejo²,

López-Barrio³

et al. 2008

IJES

View full text Add to dashboard Cite

show abstract

“…Moreover, when working with the register file, there is no way to recover data from memory without extra accesses to the cache, and something has to be done in the unused registers to prevent the information from being lost. In fact, various authors have suggested that by turning these unused registers into a low-power state (drowsy state), the power consumption can be reduced to a minimum without data loss (Hanson et al, 2001).…”

Section: Proposed Architectural Extensionsmentioning

confidence: 99%

Energy-aware compilation and hardware design for VLIW embedded systems

Ayala

López‐Vallejo

Atienza

et al. 2007

IJES

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Tomorrow's embedded devices need to run multimedia applications demanding high computational power with low energy consumption constraints. In this context, the register file is a key source of power consumption and its inappropriate design and management severely affects system power. In this paper, we present a new approach to reduce the energy of shared register files in forthcoming embedded VLIW processors running real-life applications up to 60% without performance penalty. This approach relies on limited hardware extensions and a compiler-based energy-aware register assignment algorithm to deactivate at run-time parts of the register file (i.e., sub-banks) in an independent way.

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“…Moreover, when working with the register file, there is no way to recover data from memory without extra accesses to the cache. For register files, various authors have suggested that turning these unused registers into a low-power state (drowsy state), the power consumption can be reduced to a minimum without data loss [44].…”

Section: Register File Hardware Modificationsmentioning

confidence: 99%

Joint hardware–software leakage minimization approach for the register file of VLIW embedded architectures

Atienza

Raghavan

Ayala³

et al. 2008

Integration

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New applications demand very high processing power when run on embedded systems. Very Long Instruction Word (VLIW) architectures have emerged as a promising alternative to provide such processing capabilities under the given energy budget. However, in this new VLIW-based architectures, the register file is a very critical contributor to the overall power consumption and new approaches have to be proposed to reduce its power while preserving system performance. In this paper, we propose a novel joint hardware-software approach that reduces the leakage energy in the register files of these embedded VLIW architectures. This approach relies upon an energy-aware register assignment method and a hardware support that creates sub-banks in the global register file that can be switched on/off at run time. Our results indicate energy savings in the register file, after considering the overhead of the added extra hardware, up to 50% for modern multimedia embedded applications without performance degradation. We illustrate this approach using real-life applications running on these processors. We also illustrate the tradeoff between the area overhead vs. the gains in the leakage energy for the different strategies. r

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Static energy reduction techniques for microprocessor caches

Cited by 46 publications

References 9 publications

A hardware mechanism to reduce the energy consumption of the register file of in-order architectures

A hardware mechanism to reduce the energy consumption of the register file of in-order architectures

Energy-aware compilation and hardware design for VLIW embedded systems

Joint hardware–software leakage minimization approach for the register file of VLIW embedded architectures

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