Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line

Wei, Ye; Yu, Bei; Pan, David Z.; Ban, Yongchan; Liebmann, Lars W.

doi:10.1145/2742060.2742084

Cited by 35 publications

(10 citation statements)

References 21 publications

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“…Standard cell designers can address this issue by I/O pin optimization with the assistance from pin access optimization and evaluation engine [63], [72]. A detailed placement engine can mitigate routing resource competitions by intelligent cell spreading [58].…”

Section: Pin Access and Routing Co-optimizationmentioning

confidence: 99%

Toward Unidirectional Routing Closure in Advanced Technology Nodes

Pan

2017

IPSJ Transactions on System LSI Design Methodology

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Abstract:In advanced technology nodes, unidirectional layout is strongly preferred for high-density metal layers for better manufacturability. The lithography printing of unidirectional layout can be tightly controlled with illumination source optimization and resolution enhancement techniques. Meanwhile, with the unidirectional layout, self-aligned double and quadruple patterning can be applied to achieve finer pitches beyond the resolutions limits of 193 nm lithography tools. However, unidirectional layout style introduces significant impacts on the physical design flow. Notably, unidirectional routing limits the standard cell pin accessibility, which makes manual cell layout design and optimization more and more challenging under modern standard cell architecture. In the routing phase, routing densities and resource competitions on lower metal layers are becoming increasingly high, where intelligent approaches are needed to resolve routing resource competitions for unidirectional routing closure. Moreover, post-routing optimization is inevitable to avoid significant engineering-changing-efforts for unidirectional routing under advanced manufacturing constraints. In this paper, we present a holistic approach, including standard pin access evaluation/optimization, pin access and routing co-optimization and post-routing optimization, to enable unidirectional routing closure in advanced technology nodes.

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Section: Pin Access and Routing Co-optimizationmentioning

confidence: 99%

Toward Unidirectional Routing Closure in Advanced Technology Nodes

Pan

2017

IPSJ Transactions on System LSI Design Methodology

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“…Although manual standard cell designs are still widely used to get the best performance/area/power, etc. [7,8], automatic standard cell synthesis has been actively studied to achieve comparable design quality and shorter turnaround time [9][10][11][12][13][14][15]. Taylor et al [9] and Maly et al [10] have early studies on applying regular layout patterns in standard cell synthesis.…”

Section: Dfm In Standard Cell Designmentioning

confidence: 99%

Design for manufacturability and reliability in extreme-scaling VLSI

Roy

et al. 2016

Sci. China Inf. Sci.

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In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore's law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.

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“…A systematic library regularity design and robustness evaluation framework will be crucial to provide good starting point of SC design and quick feedback on the quality evaluation under MPL constraints [36]. Additional metal layers for intra-cell routing, such as M0 or Mint [2,3], may be introduced to reduce the usage of Metal-2 wires for SC design, which is crucial for better local pin access during the routing stage.…”

Section: Future Cell Architecturementioning

confidence: 99%

Pushing multiple patterning in sub-10nm

Pan

Liebmann

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Due to elongated delay of extreme ultraviolet lithography (EUVL), the semiconductor industry has been pushing the 193nm immersion lithopgrahy using multiple patterning to print critical features in 22nm/14nm technology nodes and beyond. Multiple patterning lithography (MPL) poses many new challenges to both mask design and IC physical design. The mask layout decomposition problem has been extensively studied, first on double patterning, then on triple or even quadruple patterning. Meanwhile, many studies have shown that it is very important to consider MPL implications at early physical design stages so that the overall design and manufacturing closure can be reached. In this paper, we provide a comprehensive overview on the state-of-the-art research results for MPL, from synergistic mask synthesis to physical design. We will also discuss the open problems as to pushing multiple patterning in sub-10nm.

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Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line

Cited by 35 publications

References 21 publications

Toward Unidirectional Routing Closure in Advanced Technology Nodes

Toward Unidirectional Routing Closure in Advanced Technology Nodes

Design for manufacturability and reliability in extreme-scaling VLSI

Pushing multiple patterning in sub-10nm

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