Stage-Dependent DSP Operation Range Clipping-Induced Bit Resolution Reductions of Full Parallel 64-Point FFTs Incorporated in FPGA-Based Optical OFDM Receivers

Analytical Solution of Stage-Dependent Bit Resolution of Full Parallel Variable Point FFTs for Real-Time DSP Implementation

“…It has been shown that the numerically identified maps enable significant reductions in FPGA logic resource usage without degrading the overall transceiver performance [21]. To further reduce the FFT DSP logic resource usage with the overall transceiver performance still being maintained, in [22], improved stage-dependent minimum bit resolution maps with further 3-bit reductions have been numerically identified by taking into account the DSP operation dynamic range-clipping technique, and the identified maps have also been experimentally verified for the 64-point FFT. In all of our previously published work [19]- [22], the stage-dependent minimum bit resolution maps are obtained using a numerical simulation-based sophisticated and time-consuming approach.…”

“…To further reduce the FFT DSP logic resource usage with the overall transceiver performance still being maintained, in [22], improved stage-dependent minimum bit resolution maps with further 3-bit reductions have been numerically identified by taking into account the DSP operation dynamic range-clipping technique, and the identified maps have also been experimentally verified for the 64-point FFT. In all of our previously published work [19]- [22], the stage-dependent minimum bit resolution maps are obtained using a numerical simulation-based sophisticated and time-consuming approach. The approach may, however, not be practically feasible for use in extremely large-and/or dynamically variable-point FFTs that are highly desirable for future converged dynamic and flexible networks.…”

“…The validity and robustness of the developed analytical solution are rigorously verified, both numerically and experimentally, over intensity modulation and direct detection (IMDD) optical OFDM transmission systems subject to a wide range of various operation parameters. In comparison with our previously published work [19]- [22], the unique advantages associated with the developed analytical solution are summarized as followings:…”

“…Our investigations show that >31% savings in FPGA arithmetic logic resource usage is achievable for the 128point FFT compared with the corresponding Spiral FPGA design. In summary, in comparison with the simulation-based sophisticated and time-consuming approach reported in [22], the analytical solution greatly eases the real-time practical FFT DSP design, considerably decreases the DSP complexity, and can serve as an effective tool for maximizing the overall system performance by making full use of available transceiver/system design parameters.…”

“…At each stage both the twiddle factor bit resolution and the output bit resolution are independently adjustable. As the search method using the bit resolution maps reported in [22] is sufficiently easy in obtaining minimum twiddle factor resolution bits, in this paper, special attention is thus given to stage-dependent output bit resolutions for the third stage and beyond, because the first and second stages just have addition and subtraction operations only.…”