Analytical Solution of Stage-Dependent Bit Resolution of Full Parallel Variable Point FFTs for Real-Time DSP Implementation

Zhang, J. J.; Wang, W. L.; Giddings, R. P.; Zhang, Q. W.; Peng, Junjie; Chen, J.; Tang, J. M.

doi:10.1109/jlt.2018.2870144

Cited by 3 publications

(3 citation statements)

References 24 publications

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“…To verify the performance of the layered LDPC decoder with the proposed architecture in OFDM-PON, experiments are undertaken by an FPGA-based OFDM-PON platform previously used in [23][24][25][26][27] and an FPGA-based LDPC decoder, as shown in Figure 7. In this paper, two Xilinx FPGA boards (ML605) with Virtex-6 XC6VLX240T are used in the implementation of the OFDM-PON platform.…”

Section: Methodsmentioning

confidence: 99%

“…Then, a 16sample cyclic prefix (CP) was inserted for each OFDM symbol, and a synchronization Afterwards, the data are subjected to a 64-point IFFT operation to form M OFDM symbols. The optimization of the IFFT/FFT operation can be referred to in our previous work [27]. Since we designed a complete LDPC codeword to be carried by a single OFDM frame, the size of M was determined by the code length (2304) and the number of valid bits (27 × n, n is 4 for 16-QAM or 6 for 64-QAM) carried by a single OFDM symbol.…”

Section: Methodsmentioning

confidence: 99%

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Efficient Pipeline Conflict Resolution for Layered QC-LDPC Decoders in OFDM-PON

Wang,

Xu,

Chen

et al. 2024

Photonics

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The high standard of communication quality in optical access networks makes forward error correction (FEC) schemes, such as LDPC, an integral part of the system. However, pipeline conflict arising from data dependencies is a common issue encountered in the hardware implementation of layered QC-LDPC decoders. This paper proposes an efficient layered decoding architecture to reduce pipeline conflicts without introducing stall cycles. It can solve some of the pipeline conflicts by flexibly reordering the processing order of inter-layer and intra-layer submatrices offline. In addition, the patch method, based on variable-to-check messages, allows for the delayed use of gains between layer iterations, which can further minimize the performance loss caused by the remaining pipeline conflicts. The experimental results on the LDPC code of the IEEE802.16 standard in the OFDM-PON system demonstrate that the proposed architecture has sensitivity improvements of 0.125 dBm and 0.375 dBm, respectively, compared with our previous work and the method described in the other work. The optimized architecture improves the reliability of the decoder and can also make a contribution to efficient PON systems.

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Section: Methodsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Efficient Pipeline Conflict Resolution for Layered QC-LDPC Decoders in OFDM-PON

Wang,

Xu,

Chen

et al. 2024

Photonics

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“…Further improvements in the energy consumption efficiency of OFDM-PONs based on intensity modulation and direct detection (IMDD) are also achievable when the dynamic SNR management is conducted in conjunction with adaptive modulation [8]. Furthermore, Hu et al [3] T proposed and experimentally verified a minimum bit resolution map for the full-parallel pipelined 64-point FFT [9], and an analytical solution has subsequently been derived in [10], which significantly eases the practical utilization of the bit resolution map as sophisticated numerical simulations are no longer needed for a specific application scenario. Apart from the abovementioned effort in making the OFDMassociated core FFT/IFFT operation more power efficient, in the network layer, several energy-saving schemes based on sleep-mode, doze-mode and dynamic bandwidth allocation (DBA) algorithm can also be used in the OFDM-PONs in low traffic load situations [11], [12].…”

Section: Introductionmentioning

confidence: 99%

A Clock-Gating-Based Energy-Efficient Scheme for ONUs in Real-Time IMDD OFDM-PONs

Zhang

Zhao

Huang

et al. 2020

J. Lightwave Technol.

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Design of Spectrum Processing Chiplet Based on FFT Algorithm

2023

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With the rapid development of electronic information and computer science, the fast Fourier transform (FFT) has played an increasingly important role in digital signal processing (DSP). This paper presented a spectrum processing chiplet design method to solve slow speed, low precision, and low resource utilization in spectrum processing of general-purpose spectrum chips and field programmable gate array (FPGA). To realize signal processing, the Radix-2 4096-point FFT algorithm with pipeline structure is used to process spectral signals extracted from the time domain. To reduce the harm caused by spectrum leakage, a windowing module is added to optimize the input data, and the clock gating unit (CGU) is used to perform low-power management on the entire clock reset. The result shows the chiplet takes 0.368 ms to complete a 4096-point frequency sweep under a clock frequency of 61.44 MHz. The chiplet significantly improves speed and accuracy in spectrum processing, which has great application potential in wireless communication.

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Analytical Solution of Stage-Dependent Bit Resolution of Full Parallel Variable Point FFTs for Real-Time DSP Implementation

Abstract: Peer reviewed versionCyswllt i'r cyhoeddiad / Link to publication Dyfyniad o'r fersiwn a gyhoeddwyd / Citation for published version (APA):Zhang,

Cited by 3 publications

References 24 publications

Efficient Pipeline Conflict Resolution for Layered QC-LDPC Decoders in OFDM-PON

Efficient Pipeline Conflict Resolution for Layered QC-LDPC Decoders in OFDM-PON

A Clock-Gating-Based Energy-Efficient Scheme for ONUs in Real-Time IMDD OFDM-PONs

Design of Spectrum Processing Chiplet Based on FFT Algorithm

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