Stacked SiGe nanosheets p-FET for Sub-3 nm logic applications

Abstract

The fabrication of vertically stacked SiGe nanosheet (NS) field-effect transistors (FETs) was demonstrated in this study. The key process technologies involved in this device fabrication are low pressure chemical vapor deposition SiGe/Si multilayer epitaxy, selective etching of Si layers over SiGe layers using tetramethyl-ammonium-hydroxide wet solution, and atomic layer deposition of Y2O3 gate dielectric. For the fabricated stacked SiGe NS p-GAAFETs with a gate length of 90 nm, ION/IOFF ratio of around 5.0 × 105 and subthreshold swing of 75 mV/dec were confirmed via electrical measurements. Moreover, owing to its high quality of Y2O3 gate dielectric, the device showed a very small drain-induced barrier-lowering phenomenon. These designs can improve the gate controllability of channel and device characteristics.

Self-Induced Ge-Doped HfO2 Applied to Ge Stacked Nanowires Ferroelectric Gate-All-Around Field-Effect Transistor with Steep Subthreshold Slope Under O3 Treatment with GeO2 as Interfacial Layer

“…15 The different thicknesses of Al 2 O 3 and HfO 2 were also investigated in this work because the amount of Ge in HfO 2 has an effect on ferroelectricity. Recently, stacked gate-all-around fieldeffect transistors (GAAFETs) including multiple-channel structures of nanosheets [16][17][18][19] and nanowires (NWs) [20][21][22][23] have been extensively considered to boost the driving current and overcome the issue of short-channel effects to continue Moore's law to future technology nodes, owing to their excellent electrostatic characteristics. Ge diamond-shaped NW with (111) channel surfaces along 〈110〉 direction shows excellent device performance with greatest electrostatic control and high I on /I off .…”