Stability and variability enhancement of 9T SRAM cell for subthreshold operation

Anand, Nitin; Pal, Soumitra; Islam, Aminul

doi:10.1109/indicon.2014.7030462

Cited by 4 publications

(2 citation statements)

References 14 publications

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“…Karthika and SivaMangai (2016) showed that 9T SRAM array with bit interleaving architecture consumes low power with good stability compared to the shared wordline architecture using 6T SRAM cell. Anand et al (2014) proposed two different optimization techniques for more reliable and stable 9T SRAM. By using these two techniques namely, Cell Content Body Bias (CCBB) and Dynamic threshold MOS (DTMOS) for sub-threshold region, it is found to have better RSNM at 0.35V, 41.8% bottom read access time, narrower spread in write access and read access time as 8 and 53.01% respectively over conventional 9T cell.…”

Section: Literature Reviewmentioning

confidence: 99%

Design and Analysis of SRAM Cell for Smart Application

Praveen¹,

Singh²

2022

Journal of Computer Science

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In today's circuit technology, power consumption and savings are key concerns. The driving reasons behind these innovations are portable devices that require high throughput and low power dissipation, such as computers, phones, and Personal Digital Assistants (PDAs). In portable devices, reducing or decreasing IC dissipated power through design optimization is a big problem, and restricted battery lifespan places very severe restrictions on overall power usage. In this study SRAM circuit for smart applications has been investigated using various factors such as write, read, dynamic, static power with voltage and temperature. The power consumption analysis is the most essential criteria for memory design. Because data stability is a critical concern, affecting both the read and write operations. The implemented 9T SRAM in this study is more efficient than the other SRAM in terms of power usage. When compared with the existing SRAM circuits taken for comparison of different parameters, the proposed 9T SRAM, circuit uses less than 28.2% write power, while it uses about the same for read operation. The data retention voltage for both circuits is 0.29 V, which is utilized to store the data in the circuit. The 32 nm Bulk CMOS process technology from PTM files is used for designing and analysis.

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Section: Literature Reviewmentioning

confidence: 99%

Design and Analysis of SRAM Cell for Smart Application

Praveen¹,

Singh²

2022

Journal of Computer Science

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“…1. The 6T cell has a high power consumption [1, 2]. According to the literature, the most effective method for reducing power consumption is cell design in sub‐threshold region on lower VDDs [3].…”

Section: Introductionmentioning

confidence: 99%

A new 7T SRAM cell in sub‐threshold region with a high performance and small area with bit interleaving capability

Nobakht

Niaraki

2019

IET Circuits, Devices & Systems

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In recent years, many researches have been conducted on 6T static memory performance improvements and strengthen it against soft error in sub-threshold region. These studies finally result in some SRAM cell designs with the proper performance in bit-interleaving structure and sub-threshold region in cost of more area consumption. This study presents a new bit-interleaving 7T SRAM cell which occupies less area consumption and has a better performance when compared with other 9T, 10, and 12T bit-interleaving cells. The suggested 7T cell is simulated with HSPICE in 32 nm technology and with multi-Vt transistors considering LP, HP, and standard models for HVt, LVt, and SVt transistors, respectively. The simulation results demonstrate the performance superiority of authors' proposed cell compared with its counterparts. Moreover, the simulation results (VDD = 0.5 V) show the suggested cell in comparison with conventional 6T cell improves read, hold, and write power consumptions 91.42, 91.93, and 68.7%, respectively. Also, cell stability (RSNM) and write margin (WM) parameters improve 172 and 67.2%, respectively.

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