Stability and accuracy analysis of power hardware in the loop system with different interface algorithms

Hatakeyama, Tomoyuki; Riccobono, Antonino; Monti, Antonello

doi:10.1109/compel.2016.7556671

Cited by 28 publications

(12 citation statements)

References 13 publications

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“…A number of studies have investigated the stability of PHIL simulations [11][12][13][14][15], where the main findings include the establishment of stability thresholds imposed by the interface algorithms used for the PHIL implementation. Improvements to alleviate the identified stability limitations have been proposed in [12,16,17].…”

Section: Phil Initialization and Synchronizationmentioning

confidence: 99%

Initialization and Synchronization of Power Hardware-In-The-Loop Simulations: A Great Britain Network Case Study

Guillo-Sansano¹,

Syed²,

Roscoe³

et al. 2018

Energies

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The hardware under test (HUT) in a power hardware in the loop (PHIL) implementation can have a significant effect on overall system stability. In some cases, the system under investigation will be unstable unless the HUT is already connected and operating. Accordingly, initialization of the real-time simulation can be difficult, and may lead to abnormal parameters of frequency and voltage. Therefore, a method to initialize the simulation appropriately without the HUT is proposed in this contribution. Once the initialization is accomplished a synchronization process is also proposed. The synchronization process depends on the selected method for initialization and therefore both methods need to be compatible. In this contribution, a recommended practice for the initialization of PHIL simulations for synchronous power systems is presented. Experimental validation of the proposed method for a Great Britain network case study demonstrates the effectiveness of the approach.

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Section: Phil Initialization and Synchronizationmentioning

confidence: 99%

Initialization and Synchronization of Power Hardware-In-The-Loop Simulations: A Great Britain Network Case Study

Guillo-Sansano¹,

Syed²,

Roscoe³

et al. 2018

Energies

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“…GOL DIM becomes zero and, therefore, never crosses the −1 point in the Nyquist diagram, thus, guaranteeing absolute stability. As done in [20]- [21], considerations about the accuracy of the PHiL system can be formulated, by evaluating voltages and currents of the PHiL system with DIM IA on the simulation side ("A" subscript) and on the DUT side ("B" subscript) compared to those of the NCS picked as test case reference. The equations in Table I are derived by inspection of Fig.…”

Section: Power Hardware In the Loop -Interface Algorithmmentioning

confidence: 99%

“…However, this method requires knowledge of the impedance of the DUT. The WSI technique is suggested in [19]- [21] as a method to identify the DUT impedance and it is here integrated in an existing PHiL simulation setup to improve its stability and accuracy.…”

mentioning

confidence: 99%

Online Parametric Identification of Power Impedances to Improve Stability and Accuracy of Power Hardware-in-the-Loop Simulations

Riccobono

Liegmann

Pau

et al. 2017

IEEE Trans. Instrum. Meas.

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“…However, a common challenge is the lack of a flexible and practical approach to reproduce accurately the dynamic effects introduced by long HVDC cables. In order to improve the fidelity of laboratory tests this paper aims to reduce the dynamics missing due to poor modeling of the line/cable on HVDC systems with an approach based on Power Hardware in the Loop (PHiL) [4], [5]. This is done by introducing a physical implementation a single conductor model from the Universal Line Model (SC-ULM) [6] on a controlled voltage source that can represent dynamics with a limited frequency bandwidth (BW).…”

Section: Introductionmentioning

confidence: 99%

An approach for small scale power hardware in the loop emulation of HVDC cables

Sánchez

D’Arco

Holdyk

et al. 2018

2018 Thirteenth International Conference on Ecological Vehicles and Renewable Energies (EVER)

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Long HVDC cables are difficult to emulate in laboratory settings due their complex behaviour and fast transient response. This paper presents the methodology for the design and the laboratory implementation of a HVDC cable emulator with a Power Hardware in the Loop approach. The cable representation in the real time simulation is based on the Universal Line Model present in state of the art software for electromagnetic transients analysis. The proposed cable emulation reproduces the cable dynamics up to the kHz range with present commercially available hardware. Moreover, this approach offers a higher flexibility in adapting the cable characteristics and length compared to other existing alternatives.

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Stability and accuracy analysis of power hardware in the loop system with different interface algorithms

Cited by 28 publications

References 13 publications

Initialization and Synchronization of Power Hardware-In-The-Loop Simulations: A Great Britain Network Case Study

Initialization and Synchronization of Power Hardware-In-The-Loop Simulations: A Great Britain Network Case Study

Online Parametric Identification of Power Impedances to Improve Stability and Accuracy of Power Hardware-in-the-Loop Simulations

An approach for small scale power hardware in the loop emulation of HVDC cables

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