SSTL I/O Standard based environment friendly energyl efficient ROM design on FPGA

Bansal, Meenakshi; Bansal, Neelam; Saini, Rishita; Pandey, Bishwajeet; Kalra, Lakshay; Hussain, Dil Muhammad Akbar

doi:10.1109/efea.2014.7059947

Cited by 14 publications

(7 citation statements)

References 16 publications

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“…In [8] researchers used Virtex-6 FPGA to design four-bit unsigned up counter by enabling clock and with an asynchronous clear. In [9] authors interfaced Random Access Memory (ROM) design on Virtex-6 FPGA.…”

Section: Related Workmentioning

confidence: 99%

Power Efficient Frequency Scaled and Thermal-Aware Control Unit Design on FPGA

Kumar

Ahmad

Pandey

et al. 2019

IJITEE

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These works describe the implementation of a control unit which is an important part of Central Processing Unit (CPU) with the Field Programmable Gate Array (FPGA). In this work a frequency scaled and thermal aware energy-efficient control unit is designed with the help of 28 nanometer (nm) technology based FPGA. Frequency varies from 100MHz to 5GHz and the rise in frequency also gives rise in power consumption of control unit with FPGA. The thermal properties of FPGA also increase with increment in frequency. This whole experiment is done on Xilinx 14.1 ISE Design Suit and it isobserved that lower the frequency, lower will be the power consumption of FPGA.

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Section: Related Workmentioning

confidence: 99%

Power Efficient Frequency Scaled and Thermal-Aware Control Unit Design on FPGA

Kumar

Ahmad

Pandey

et al. 2019

IJITEE

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“…Authors used various SSTL I/O standard to calculate the power of device [10]. An energy-efficient Read-Only Memory (ROM) is designed by authors using various SSTL I/O standard techniques [11]. Power efficient and thermal aware adder circuit is designed on 65 nm FPGA using different HSTL I/O standard [12].…”

Section: Related Workmentioning

confidence: 99%

HSTL and HSUL I/O Standard Based Energy-Efficient Control Unit Circuit Design on FPGA

Kumar¹,

Pandey²

2019

GJECS

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World is facing a huge problem of power deficiency. That's why power and energyefficient devices are getting more attention these days. This work highlights the energy-efficient control design implementation on 28nm technology Artix-7 Field Programmable Gate Array (FPGA). The implementation is done on the Vivado 2014.2 Design Suite. In this work, the Input/Output (I/O) Standard is varied at both input and output end of control unit circuit for calculating the power utilization of the control unit circuit with 28-nm FPGA. It is observed that High-Speed Unterminated Logic (HSUL_12) I/O Standard consumes the least amount of power when the control unit circuit is implemented on 28-nm FPGA.

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“…In this work authors worked on IO standards of FPGA to study the power consumption of Random Access Memory (RAM). By using Virtex-6 FPGA, authors interfaced RAM to minimize its power consumption [14]. For real-time simulation photovoltaic modules are designed by the authors with the help of FPGA [15].…”

Section: Related Workmentioning

confidence: 99%

Frequency Scaling Based Power Efficient Current Source Design on FPGA

Kaur,

Kumar,

Gandhi

et al. 2019

IJEAT

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 Abstract: Power deficiency is one of the major problems that the whole world is facing now. This is happening because of the immense increase in the world's population and the global increase of industrialization. So in order to minimize the consumption of power, an energy efficient current source is designed with the help of Field Programmable Gate Array (FPGA). This work gives light on how the power variation takes place in a current source with an increase in frequency value. In this research work, the current source is implemented on 28 nanometers (nm) Airtx-7 FPGA. The work is demonstrated on Xilinx 14.1 ISE simulator. VHSIC Hardware Description Language (VHDL) is used for writing the code of current source. The frequency of current source with Airtx-7 FPGA is increased from 100MHz to 5GHz. It is analyzed that the total power consumption is less as the value of frequency is low. So it is always advisable to operate the device at a lower frequency range in orderto save more energy.

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SSTL I/O Standard based environment friendly energyl efficient ROM design on FPGA

Cited by 14 publications

References 16 publications

Power Efficient Frequency Scaled and Thermal-Aware Control Unit Design on FPGA

Power Efficient Frequency Scaled and Thermal-Aware Control Unit Design on FPGA

HSTL and HSUL I/O Standard Based Energy-Efficient Control Unit Circuit Design on FPGA

Frequency Scaling Based Power Efficient Current Source Design on FPGA

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