SRAM Programmable FPGAs

Trimberger, Steve

doi:10.1007/978-1-4615-2742-8_2

Cited by 10 publications

(31 citation statements)

References 40 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The up-front NRE cost ensured that FPGAs were more cost effective than ASICs at some volume [38]. FPGA vendors touted this in their ''crossover point,'' the number of units that justified the higher NRE expense of an ASIC.…”

Section: Preamble: What Was the Big Deal About Fpgas?mentioning

confidence: 99%

“…A PAL device, as depicted in Fig. 3, consists of a twolevel logic structure [6], [38]. Inputs are shown entering at the bottom.…”

Section: B Fpga Versus Palmentioning

confidence: 99%

“…A modern reader may not recognize most of the companies or product names in Section III and in the FPGA genealogical tree in Fig. 5 [6], [38]. Many of the companies simply vanished.…”

Section: Interlude: Shakeout In Fpga Businessmentioning

confidence: 99%

See 2 more Smart Citations

Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology

Trimberger

2015

Proc. IEEE

181

View full text Add to dashboard Cite

Since their introduction, field programmable gate arrays (FPGAs) have grown in capacity by more than a factor of 10 000 and in performance by a factor of 100. Cost and energy per operation have both decreased by more than a factor of 1000. These advances have been fueled by process technology scaling, but the FPGA story is much more complex than simple technology scaling. Quantitative effects of Moore's Law have driven qualitative changes in FPGA architecture, applications and tools. As a consequence, FPGAs have passed through several distinct phases of development. These phases, termed ''Ages'' in this paper, are The Age of Invention, The Age of Expansion and The Age of Accumulation. This paper summarizes each and discusses their driving pressures and fundamental characteristics. The paper concludes with a vision of the upcoming Age of FPGAs.

show abstract

Section: Preamble: What Was the Big Deal About Fpgas?mentioning

confidence: 99%

“…A PAL device, as depicted in Fig. 3, consists of a twolevel logic structure [6], [38]. Inputs are shown entering at the bottom.…”

Section: B Fpga Versus Palmentioning

confidence: 99%

See 1 more Smart Citation

Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology

Trimberger

2015

Proc. IEEE

181

View full text Add to dashboard Cite

show abstract

“…A field-programmable gate array (FPGA) is a semiconductor device that can be programmed after manufacture to perform a specific application design, typically specified as a digital logic system [43]. A taxonomy of FPGAs commonly starts with the program storage technology (Fig.…”

Section: Introduction a Fpgas And Programming Technologymentioning

confidence: 99%

“…SRAM-programmed FPGAs store their configuration data in internal volatile memory cells distributed throughout the device. These are generally not SRAM cells, but are more similar to static latch cells [43]. Xilinx's 7-Series and Altera's Stratix-5 are examples of popular SRAM-based FPGAs.…”

Section: Introduction a Fpgas And Programming Technologymentioning

confidence: 99%

FPGA Security: Motivations, Features, and Applications

2014

View full text Add to dashboard Cite

show abstract

Semi‐tensor product‐based algebra‐logic mixed representation and fault diagnosis for a class of gate networks

Liu

Shen

Moschoyiannis

et al. 2023

Asian Journal of Control

View full text Add to dashboard Cite

This article studies an algebra‐logic mixed representation of gate networks and its application to stuck‐at fault diagnosis. First, the gate network is characterized through a logic expression of disjoint sum‐of‐products, and the system structure of the gate network is described based on 2‐to‐1 multiplexers. Then, by resorting to the semi‐tensor product of matrices, a novel algebra‐logic mixed representation is proposed for the gate network through its logic expression and system structure. Furthermore, a novel stuck‐at fault diagnosis algorithm for the gate network is presented, where the stuck‐at fault testability of the gate network is equivalent to the solution existence of the system of linear equations. Finally, the fault diagnosis of the 4‐bit carry look‐ahead adder is carried out to demonstrate the effectiveness and feasibility of the proposed theoretical approach and algorithms.

show abstract

SRAM Programmable FPGAs

Cited by 10 publications

References 40 publications

Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology

Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology

FPGA Security: Motivations, Features, and Applications

Semi‐tensor product‐based algebra‐logic mixed representation and fault diagnosis for a class of gate networks

Contact Info

Product

Resources

About