SRAM cell stability under the influence of parasitic resistances and data holding voltage as a stability prober

Kato, Hiroaki; Matsui, M.; Sato, K.; Shibata, H.; Hashimoto, Kenji; Ootani, T.; Ochii, K.

doi:10.1109/4.551915

Cited by 6 publications

(3 citation statements)

References 7 publications

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“…Given that cell storage nodes were wired through a hierarchical complementary metal-oxide semiconductor (CMOS) pass-gate network, such method is not applicable to industrial designs. These techniques do not require extra test circuitry as they rely on the tendency of weaker SRAM cells to lose stability at the reduced power supply voltage faster than healthy cells [10]. This results in an insufficient number of data points for failure analysis of large cache memories.…”

Section: Introductionmentioning

confidence: 99%

“…Consequently, SRAM cell stability test techniques are usually based on data retention and/or low-voltage test techniques. These techniques do not require extra test circuitry as they rely on the tendency of weaker SRAM cells to lose stability at the reduced power supply voltage faster than healthy cells [10]. Although useful for testing purposes, these techniques do not provide the SNM value and since each cell must be accessed at various delay rates, a large amount of time is required to test each integrated circuit.…”

Section: Introductionmentioning

confidence: 99%

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Alternate characterization technique for static random‐access memory static noise margin determination

Merino

Bota

Picos

et al. 2012

Circuit Theory & Apps

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The cell static noise margin (SNM) is widely used as a stability criterion for static random-access memory cells design. This parameter is typically determined through electrical simulations since direct experimental characterization of SNM is not achievable.In this work, we present a methodology that provides an indirect measurement of the SNM on a per-cell basis for six-transistor SRAMs. It is based on combining an Adaptive Neuro-Fuzzy Inference System (ANFIS) with circuit-level cell experimentally measurable parameters as input variables to the tool. We show that it is possible to obtain the SNM for individual memory cells using the same experimental setup and data than that required for shmoo plot measurements. Results confirm that the SNM can be experimentally estimated with a relative error compared with electrical simulations that is below 0.5%.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Alternate characterization technique for static random‐access memory static noise margin determination

Merino

Bota

Picos

et al. 2012

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…This dra weighed against the improvement performance. The hold stability [5] limits the vol and therefor largely impacts th Optimization focuses on improvi subject to mismatch variations [6]. the cross-coupled inverter pair an access transistor.…”

Section: Relevance Of Memories At Ntvmentioning

confidence: 99%

Resolving the memory bottleneck for single supply near-threshold computing

Gemmeke

Sabry

Stuijt

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-This paper focuses on a review of state-of-the-art memory designs and new design methods for near-threshold computing (NTC). In particular, it presents new ways to design reliable low-voltage NTC memories cost-effectively by reusing available cell libraries, or by adding a digital wrapper around existing commercially available memories. The approach is based on modeling at system level supported by silicon measurement on a test chip in a 40nm low-power processing technology. Advanced monitoring, control and run-time error mitigation schemes enable the operation of these memories at the same optimal near-V t voltage level as the digital logic. Reliability degradation is thus overcome and this opens the way to solve the memory bottleneck in NTC systems. Starting from the available 40 nm silicon measurements, the analysis is extended to future 14 and 10 nm technology nodes.

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Sensitivity of static noise margins to random dopant variations in 6-T SRAM cells

Oniciuc

Andrei

2008

Solid-State Electronics

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SRAM cell stability under the influence of parasitic resistances and data holding voltage as a stability prober

Cited by 6 publications

References 7 publications

Alternate characterization technique for static random‐access memory static noise margin determination

Alternate characterization technique for static random‐access memory static noise margin determination

Resolving the memory bottleneck for single supply near-threshold computing

Sensitivity of static noise margins to random dopant variations in 6-T SRAM cells

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