SRAM-Based Unique Chip Identifier Techniques

Chellappa, Srivatsan; Clark, Lawrence T.

doi:10.1109/tvlsi.2015.2445751

Cited by 18 publications

(6 citation statements)

References 21 publications

(23 reference statements)

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“…Due to manufacturing process variation, every transistor or wire in a physical device has slightly different characteristics. These differences lead to measurable differences in responses of two PUF instances to the same challenge, making possible using the PUF as a unique device "fingerprint" [16], [17].…”

Section: Introductionmentioning

confidence: 99%

CRC-PUF: A Machine Learning Attack Resistant Lightweight PUF Construction

Dubrova

Naslund

Degen

et al. 2019

2019 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW)

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Adversarial machine learning is an emerging threat to security of Machine Learning (ML)-based systems. However, we can potentially use it as a weapon against ML-based attacks. In this paper, we focus on protecting Physical Unclonable Functions (PUFs) against ML-based modeling attacks. PUFs are an important cryptographic primitive for secret key generation and challenge-response authentication. However, none of the existing PUF constructions are both ML attack resistant and sufficiently lightweight to fit low-end embedded devices. We present a lightweight PUF construction, CRC-PUF, in which input challenges are de-synchronized from output responses to make a PUF model difficult to learn. The de-synchronization is done by an input transformation based on a Cyclic Redundancy Check (CRC). By changing the CRC generator polynomial for each new response, we assure that success probability of recovering the transformed challenge is at most 2 −86 for 128-bit challenges and responses.

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Section: Introductionmentioning

confidence: 99%

CRC-PUF: A Machine Learning Attack Resistant Lightweight PUF Construction

Dubrova

Naslund

Degen

et al. 2019

2019 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW)

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“…Recently, Physical Unclonable Function (PUF) has sprouted up as a promising primitive to enforce data privacy and access control to electronic devices. Among the PUF implementations [1][2][3][4][5], SRAM-based PUF (SPUF) has attracted tremendous attention. This is because SRAM, being an integral part of computer memory sub-system, plays a pivotal role in trusted computing platforms.…”

Section: Introductionmentioning

confidence: 99%

“…The exploitation of process-variation induced device mismatches in the cross-coupled inverter cell for random, unique and reliable response bit generation is detrimental to the regular memory operation, as it will result in increased parametric failures due principally to destructive read and unsuccessful write operations. Archived literatures reported wide varieties of design approaches that either improve the qualities of SPUF or harness the readability and writability of SRAM cells as data storage elements, albeit independently [5,6]. However, no design strategy has been proposed to tackle the conflicting quality requirements to unify the two different modes of operation in an SRAM cell.…”

Section: Introductionmentioning

confidence: 99%

Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions

Chang

Liu

Zhang

et al. 2016

JLPEA

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Static Random Access Memory (SRAM) has recently been developed into a physical unclonable function (PUF) for generating chip-unique signatures for hardware cryptography. The most compelling issue in designing a good SRAM-based PUF (SPUF) is that while maximizing the mismatches between the transistors in the cross-coupled inverters improves the quality of the SPUF, this ironically also gives rise to increased memory read/write failures. For this reason, the memory cells of existing SPUFs cannot be reused as storage elements, which increases the overheads of cryptographic system where long signatures and high-density storage are both required. This paper presents a novel design methodology for dual-mode SRAM cell optimization. The design conflicts are resolved by using word-line voltage modulation, dynamic voltage scaling, negative bit-line and adaptive body bias techniques to compensate for reliability degradation due to transistor downsizing. The augmented circuit-level techniques expand the design space to achieve a good solution to fulfill several otherwise contradicting key design qualities for both modes of operation, as evinced by our statistical analysis and simulation results based on complementary metal-oxide-semiconductor (CMOS) 45 nm bulk Predictive Technology Model.

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“…Among the PUF implementations [2,3,9,[28][29][30], SRAM-based PUF (SPUF) has attracted tremendous attention. This is because SRAM, being an integral part of computer memory sub-system, plays a pivotal role in trusted computing platform.…”

Section: Introductionmentioning

confidence: 99%

“…The exploitation of process-variation induced device mismatches in the cross-coupled inverter cell for random, unique and reliable response bit generation is detrimental to the regular memory operation, as it will result in increased parametric failures due principally to destructive read and unsuccessful write operations. Archived literatures reported wide varieties of design approaches that either improve the qualities of SPUF or harness the readability and writability of SRAM cell as data storage element, albeit independently [30,31]. However, no design strategy has been proposed to tackle the conflicting quality requirements to unify the two different modes of operation in an SRAM cell.…”

Section: Introductionmentioning

confidence: 99%

Design of lightweight buffer-free sram and robust ring oscillator based physical unclonable functions

Liu¹

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The master program and the research work have been a wonderful and fruitful experience. That enjoyment largely resulted from the interaction that I have had with my supervisors, the lab-mates, the university and the people who have helped me so far. First of all, I would like to express my sincere thanks and great gratitude to my supervisor, Prof Chang Chip Hong for guiding me through this program. He trusted me and encouraged me to maximize my potential. Besides teaching me the essential skills and knowledges of doing research, he also shared with me the joy of discovery and philosophy of life, which is valuable and cultivated my interest in research. It is also very very generous of him to sponsor me to attend the conference, ISCAS2017, which gave me the opportunity to interact and learn from other postgraduates and researchers. I would also like to thank my seniors Dr. Zhang Le, Dr. Cao Yuan, Dr. Sachin and Sergey for teaching the knowledges and tools about hardware security. They guided me patiently and helped me solve the problems in this projects. I would also like to thank my other team mates, Zheng Yue, Truan, Zhong Huishu, Wang Si and Zhang Yufei, who inspired and accompanied me during the research. Without them, I would not have so many ideas and achievements. I also want to thank other postgraduates and research staff, including

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SRAM-Based Unique Chip Identifier Techniques

Cited by 18 publications

References 21 publications

CRC-PUF: A Machine Learning Attack Resistant Lightweight PUF Construction

CRC-PUF: A Machine Learning Attack Resistant Lightweight PUF Construction

Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions

Design of lightweight buffer-free sram and robust ring oscillator based physical unclonable functions

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