Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL

Wang, K.J.; Swaminathan, A.; Galton, I.

doi:10.1109/isscc.2008.4523197

Cited by 56 publications

(3 citation statements)

References 19 publications

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“…A range of techniques aimed at removing the quantizer-derived phase noise have been able to attenuate these spurs [6]- [11], and much progress has been made in explaining why and how spurs occur [12]- [16]. Most significantly, the possibility of spur-free performance has been proven in the case of polynomial nonlinearities [17], [18], and record low worst-case fractional spurs have been reported [19], [20].…”

Section: Introductionmentioning

confidence: 99%

An Exposition of Fractional Spurs Resulting From Nonlinear Distortion

Donnelly¹,

Kennedy²

2021

Preprint

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The interaction between quantization noise intro-duced by the divider controller and memoryless nonlinearities in a fractional-N PLL causes fractional spurs to occur. This paper presents a comprehensive theory to explain why combinations of quantizers and memoryless nonlinearities produce fractional spurs. Necessary and sufficient conditions for spur-free behavior in the presence of an arbitrary memoryless nonlinearity or linear combinations of sets of arbitrary memoryless nonlinearities are derived. Finally, an upper limit on the number of nonlinearities for which a quantizer can exhibit spur-free performance is derived.

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Section: Introductionmentioning

confidence: 99%

An Exposition of Fractional Spurs Resulting From Nonlinear Distortion

Donnelly¹,

Kennedy²

2021

Preprint

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“…Additionally I OFFSET is gated by the reference clock. The switch SW1 remains open when I DN and I OFF-SET are active and is closed when both are silent, thus functioning in a sampleand-hold manner [3] to reduce reference spurs. The proposed PFD is capable of detecting the relative phase between CK REF and CK DIV to enable/disable I UP for negative/positive delay values respectively.…”

mentioning

confidence: 99%

28.2 A 0.29mm<sup>2</sup> frequency synthesizer in 40nm CMOS with 0.19ps<inf>rms</inf> jitter and <-100dBc reference spur for 802.11ac

Hsueh

Cho

Shen

et al. 2014

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)

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Conventional analog PLLs do not scale well with process when compared to alldigital PLLs due to several substantial building blocks such as the loop filter and charge pump (CP). To achieve the required phase noise, the in-band noise is typically suppressed by increasing CP current and loop filter size, while the outof-band noise is reduced by improving VCO tank Q; both lead to increased die area. This paper presents a fractional-N synthesizer targeting the relatively stringent phase noise requirement to support 256-QAM and MIMO in 802.11ac. It deploys the following techniques to simultaneously address requirements of compact area, low noise and fast calibration: reuse of VCO inductor area for the loop filter; a PFD and CP design that relaxes CP design constraints without sacrificing noise; inductor-less LO generation for 802.11bgn mode; and an areaefficient reference clock doubler and associated calibration scheme. The synthesizer block diagram is shown in Fig. 28.2.1. In 802.11ac/a mode a frequency tripler followed by I/Q dividers realizes the 3/2 frequency multiplication and I/Q generation. In 802.11bgn mode, an LO generation circuit performs the 2/3 frequency multiplication and I/Q generation. This frequency plan features overlapping VCO tuning ranges between 802.11ac/a (F LO =4915~5825MHz) and 802.11bgn (F LO =2412~2484MHz) modes, such that the VCO designed for 802.11ac/a can support 802.11bgn without additional tuning range.

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“…However, when a higher BW is chosen, the problem of fractional spurious signals becomes serious. The conventional method of suppressing these spurious signals is using DAC to compensate for the error on LPF [3][4]. However the DAC consumes a large area and a lot of power.…”

mentioning

confidence: 99%

A 0.3mm<sup>2</sup> 90-to-770MHz fractional-N Synthesizer for a digital TV tuner

Kondou

Matsuda

Yamazaki

et al. 2010

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

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This paper describes a 0.3mm 2 and a 90M-to-770MHz range low spurious fractional-N synthesizer, with which mobile receivers for Japanese terrestrial digital broadcasting are equipped. The synthesizer for DTV tuner needs to cover 90Mto-108MHz which is scheduled for ISDB-T sb , and 170M-to-222MHz which is scheduled for ISDB-T mm etc, and 470M-to-770MHz for ISDB-T. And the synthesizer needs a frequency resolution of 1/7MHz to receive each segment. In addition, it is demanded that the synthesizer minimize the macro area to reduce costs while maintaining other performance (phase noise, power consumption, tracking time, etc.) from a previous work [1].It's known that a fractional-N PLL is effective to realize both a frequency resolution and small area because it can use a reference clock with higher frequency, which enables a higher loop bandwidth (BW) to be obtained, and the capacitance of a small LPF to be chosen. In particular, the synthesizer for ISDB-T/T sb /T mm tuners enables both 1/7MHz resolution and on-chip LPF using a 4MHz reference frequency, adopting a 1/4 I/Q divider for output, and choosing multiples of the 1/7 fractional ratio. However, when a higher BW is chosen, the problem of fractional spurious signals becomes serious. The conventional method of suppressing these spurious signals is using DAC to compensate for the error on LPF [3][4]. However the DAC consumes a large area and a lot of power. Another method is the FIR-Embedded noise-filtering technique [2]. Although the method is helpful in reducing fractional spurious signals, the effect is limited because a fractional spurious signal from an ΣΔ-modulator spreads to all frequencies. However, the FIR filter works as a band-eliminated filter, therefore some spurious signals remain. So we applied a "circulating register" instead of using the ΣΔ-modulator, to eliminate fractional spurious signals completely. The effect of a circulating register is shown in Fig. 13.3.1. The modulator generates a discrete quantization noise spurious signal that contains only multiples of 1/7 frequency step of the reference clock, and the 7-tap FIR filter eliminates each 1/7 frequency step of the reference clock completely. Using the architecture, maximized loop bandwidth can be achieved to reduce phase noise and to minimize the low-pass filter's capacitances without dealing with spurious signals from quantization noise. A block diagram of our fractional-N synthesizer is shown in Fig. 13.3.2.A reference feedthrough contributes to the spurious generation of the fractional-N synthesizer. We solved the issue with the switched capacitor illustrated in Fig. 13.3.3. When charge pumps operated, phase-shifted REFCLK switch φ2 is closed to charge all currents for C sc , and after operation of the charge pumps is finished, REFCLK switch φ3 is closed to send the signal to the main LPF without noise. The non-linearity of the charge pumps also contributes to spurious generation. However, it is difficult to match an up-current and a down-current to realize linearity under all PVT conditi...

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Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL

Cited by 56 publications

References 19 publications

An Exposition of Fractional Spurs Resulting From Nonlinear Distortion

An Exposition of Fractional Spurs Resulting From Nonlinear Distortion

28.2 A 0.29mm<sup>2</sup> frequency synthesizer in 40nm CMOS with 0.19ps<inf>rms</inf> jitter and <-100dBc reference spur for 802.11ac

A 0.3mm<sup>2</sup> 90-to-770MHz fractional-N Synthesizer for a digital TV tuner

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Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL

Cited by 56 publications

References 19 publications

An Exposition of Fractional Spurs Resulting From Nonlinear Distortion

An Exposition of Fractional Spurs Resulting From Nonlinear Distortion

28.2 A 0.29mm<sup>2</sup> frequency synthesizer in 40nm CMOS with 0.19ps<inf>rms</inf> jitter and &#x003C;-100dBc reference spur for 802.11ac

A 0.3mm<sup>2</sup> 90-to-770MHz fractional-N Synthesizer for a digital TV tuner

Contact Info

Product

Resources

About

28.2 A 0.29mm<sup>2</sup> frequency synthesizer in 40nm CMOS with 0.19ps<inf>rms</inf> jitter and <-100dBc reference spur for 802.11ac