Spur reduction architecture for multiphase fractional PLLs

Abstract

In this study, a multiphase fractional phase-locked loop (PLL) is presented with methods to reduce spurs. General causes of spurs are non-idealities of the phase-frequency detector (PFD) and charge pump (CP) and phase errors between the adjacent phases from the oscillator. In the architecture, the non-idealities of the PFD and CP are compensated and a phase correction circuit is added after the oscillator phase generator to reduce the phase errors, and hence minimise the spurs. Spurs may still be persistent after these modifications due to process variations and device mismatch. The effect is visible in the perturbations of the loop filter control voltage. The residual spurs are minimised by further filtering the control voltage using a moving average filter and then applying it to the oscillator. The PLL is designed in 180 nm technology and outputs a 400 MHz carrier. The highest fractional spur is decreased from −36 to −66 dBc through phase correction and control voltage filtering.

A Family of ΔΣ Modulators With High Spur Immunity and Low Folded Nonlinearity Noise When Used in Fractional- Frequency Synthesizers

“…e l s e w h e r e (24) The predicted probability distribution is compared to simulation results in Fig. 6.…”

“…In particular, let us consider the case of P1 interacting with a generic third order polynomial nonlinearity, expressed as N (x) = 3 i=0 a i x i . From the definitions in ( 10)-( 12), and considering the expression of the predicted P(•) (24), one can show that:…”

“…Let us consider first the P2 and P3 ENOP-DDSM architectures. The PNN can be evaluated from the definitions in (12) and the expression for the predicted P(•) given in (24). If we a generic fifth-order nonlinearity expressed as This article has been accepted for inclusion in a issue of this journal.…”

“…where 2π N div τ os is a phase offset that is introduced by the system and it is present in addition to the term in e acc . Such a non-zero 1 In general, a PFD/CP block exhibits both static and dynamic mismatches [10], [24]. However, previous work has shown that some typical dynamic mismatches can be approximated by a memoryless nonlinear function (see, for example [8], [11]).…”

Folded Noise Prediction in Nonlinear Fractional-N Frequency Synthesizers

“…In general, a PFD/CP block exhibits both static and dynamic mismatches[14],[15]. However, previous work has shown that some typical dynamic mismatches can be approximated by a memoryless nonlinear function[7].…”