Split ADC background self-calibration of a 16-b successive approximation ADC in 180nm CMOS

McNeill, John; David, Christopher; Coln, Michael C. W.; Chan, Ka Yan

doi:10.1109/i2mtc.2013.6555430

Cited by 4 publications

(1 citation statement)

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“…The vital problem in high-resolution SAR ADC is that the total capacitance increases exponentially with the number of bits. One method to solve this problem is to apply the split-capacitor array [1] . However, it suffers from the effects of fractional bridge capacitor, capacitor mismatch and parasitic capacitance.…”

Section: Introductionmentioning

confidence: 99%

High-resolution 1 MS/s sub-2 radix split-capacitor SAR ADC

Cao

Zhu

2017

J. Semicond.

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This paper proposes a high-resolution successive-approximation register (SAR) analog-to-digital converter (ADC) with sub-2 radix split-capacitor array architecture. The built-in redundancy of sub-2 radix architecture provides additional information in the digital calibration based on offset double injection. The calibration method is simple in structure and fast in convergence. The correction of errors in each bit is independent of those in the previous bit. A split-capacitor array is used to reduce the total capacitance especially in a high-resolution SAR ADC. An offset signal is injected by the switching scheme of capacitor array to minimize the hardware overhead. The prototype of 0.18 μm CMOS process obtains 14.46 bit ENOB and 95.65 dB SFDR after calibration. With calibration, the INL and DNL are −0.813/0.938 and −0.625/0.688, respectively.

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Section: Introductionmentioning

confidence: 99%