High-resolution 1 MS/s sub-2 radix split-capacitor SAR ADC

Cao, Chang-qi; Zhu, Zhangming

doi:10.1088/1674-4926/38/10/105008

Cited by 5 publications

(2 citation statements)

References 14 publications

(17 reference statements)

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“…The calibration performance comparison with the state-of theart ADCs is reported in Table 2. The RBWE method quickly improved SFDR to 127 dB within 4 K samples and has a better linearity enhancement than other algorithms [15][16][17][18][19][20].…”

Section: Measurement and Calibration Resultsmentioning

confidence: 99%

Rapid calibration of bits weights error for high‐resolution successive approximation register ADC

Liu

Xu²,

2019

IET Circuits, Devices & Systems

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This study presents the rapid calibration of bits weights error for an 18 bit successive approximation register analogue-to-digital converter (ADC). This calibration technique is a new hybrid algorithm. Comparing to the traditional methods, this technique significantly reduces the convergence time and improves the accuracy of bits weights error estimation. There is no wasteful time in the correction process. This proposed approach estimates the bits weights error not only from the digital-toanalogue converter capacitor mismatch, inter-stage gain error, but also the metal insulator metal (MIM), capacitor second-order voltage coefficient in the ultra-high-resolution ADC. The proposed algorithm has been verified with a test 18 bit ADC chip, where measured results show the calibration is able to improve the peak integral nonlinearity (INL), of the ADC from 29 to 1.0 LSB after calibration. Measured results also show the signal-to-noise and distortion ratio/spurious-free dynamic range of the ADC improves from 83/94 to 96/127 dB after calibration. It will be seen that the calibration is achieved in ∼4k cycles, which is more than ×25 faster than previously published algorithm.

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Section: Measurement and Calibration Resultsmentioning

confidence: 99%

Rapid calibration of bits weights error for high‐resolution successive approximation register ADC

Liu

Xu²,

2019

IET Circuits, Devices & Systems

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“…A unit cap replaced the fractional cap in Agnes et al (2008), but it caused gain error. To eliminate gain error, Cao and Zhu (2017) assumed that the unit cap of the first stage was k times as much as the second one. However, nonlinear error of ADCs was caused.…”

Section: Introductionmentioning

confidence: 99%

A design method of capacitor arrays for high-resolution SAR ADCs

Shen

Liang³

et al. 2020

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Purpose The design method of high-resolution capacitor arrays was proposed to improve the precision of successive approximation register (SAR) analog-to-digital converters (ADCs) without calibration and optimize the circuit area. Design/methodology/approach According to calculation of equivalent series capacitors and change of voltage at the comparator input node, two three-stage structures of capacitor arrays and a general design flow of the multi-stage capacitor arrays were presented. Non-ideal factors on the capacitor arrays were analyzed, and the applications of the two structures were explained based on the capacitor mismatch. Findings A multi-stage capacitor array for 16-bit SAR ADCs was implemented. The simulation result shows that its nonlinear error was less than 0.3LSB with no gain error and the sampling capacitance accounted for 92.42% of the total capacitance. Effects of capacitive parasitic and mismatch on capacitor arrays were confirmed. Originality/value The proposed method focused on capacitor arrays design of high-resolution SAR ADCs. It effectively reduced nonlinear errors, improved SNR and optimized the area of SAR ADCs. The design method was suitable for SAR ADCs with different resolutions to improve their precision.

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A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logic

Ji,

Zhou

et al. 2024

J. Semicond.

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This paper presents a 16-bit, 18-MSPS (million samples per second) flash-assisted successive-approximation-register (SAR) analog-to-digital converter (ADC) utilizing hybrid synchronous and asynchronous (HYSAS) timing control logic based on an on-chip delay-locked loop (DLL). The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter (CDAC) than the synchronous and asynchronous SAR ADC. Therefore, the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent. In addition, the foreground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter (FIR-BPF) based least-mean-square (LMS) algorithm in an off-chip FPGA (field programmable gate array). Fabricated in 40-nm CMOS process, the prototype ADC achieves 94.02-dB spurious-free dynamic range (SFDR), and 75.98-dB signal-to-noise-and-distortion ratio (SNDR) for a 2.88-MHz input under 18-MSPS sampling rate.

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High-resolution 1 MS/s sub-2 radix split-capacitor SAR ADC

Cited by 5 publications

References 14 publications

Rapid calibration of bits weights error for high‐resolution successive approximation register ADC

Rapid calibration of bits weights error for high‐resolution successive approximation register ADC

A design method of capacitor arrays for high-resolution SAR ADCs

A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logic

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