Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective

Augustine, Charles; Mojumder, Niladri N.; Fong, Xuanyao; Choday, Sri Harsha; Park, S. P.; Roy, Kaushik

doi:10.1109/jsen.2011.2124453

Cited by 46 publications

(30 citation statements)

References 25 publications

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“…An STT-RAM based cache provides an inherent trade-off between write latency and read latency. A typical transistor and magnetic tunnel junction (MTJ) cell is shown in Figure 19a [57]. The magnetic tunnel junction is the basic storage device in the spintronic field that provides data non-volatility, fast data access, and low-voltage operation.…”

Section: Spin Transfer Torque Memorymentioning

confidence: 99%

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

et al. 2017

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Abstract:In this review article for Internet of Things (IoT) applications, important low-power design techniques for digital and mixed-signal analog-digital converter (ADC) circuits are presented. Emerging low voltage logic devices and non-volatile memories (NVMs) beyond CMOS are illustrated. In addition, energy-constrained hardware security issues are reviewed. Specifically, light-weight encryption-based correlational power analysis, successive approximation register (SAR) ADC security using tunnel field effect transistors (FETs), logic obfuscation using silicon nanowire FETs, and all-spin logic devices are highlighted. Furthermore, a novel ultra-low power design using bio-inspired neuromorphic computing and spiking neural network security are discussed.

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Section: Spin Transfer Torque Memorymentioning

confidence: 99%

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

et al. 2017

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“…As a result, shown in Figure 1, hybrid main memory using DRAM and NVRAM seems to be practicable instead of pure NVRAM-based main memory in the near future. Some recent studies have introduced NVRAM-based main memory organization [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29]. However, legacy bandwidth-aware multi-core scheduling methods can not applicable with the DRAM/NVRAM hybrid main memory.…”

Section: Nvram Technologymentioning

confidence: 99%

“…Recently, the next generation Non-volatile Random Access Memory (NVRAM) technology such as PRAM, STT-MRAM and ReRAM have developed significantly [13][14][15][16]. In June 2016, for example, IBM and Samsung demonstrated MRAM cells for devices with diameters ranging from 50 down to 11 nanometers in only on nanoseconds [17].…”

Section: Introductionmentioning

confidence: 99%

“…With DRAM-only main memory, access latencies are independent of access request type (i.e., read and write). In the hybrid main memory with DRAM and NVRAM, on the contrary, access latency highly depends on the target memory [13][14][15][16]. In general, NVRAM read latency is longer than DRAM access latency and NVRAM write latency is much longer than NVRAM read latency.…”

Section: Introductionmentioning

confidence: 99%

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A Task Scheduling Scheme Considering Hybrid Main Memory and Interactive Tasks

Shin¹,

Ryu²

2016

IJCA

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“…As a result, we should adapt existing DRAM power management schemes in software to account for these variations in power consumption. Moreover, this layer should be flexible enough to deal with a predicted increase in power variation for current [28] and emerging [66,1] memory technologies (e.g., phasechange memory).…”

Section: Introductionmentioning

confidence: 99%

Variability-aware memory management for nanoscale computing

Dutt

Gupta

Nicolau

et al. 2013

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-As the semiconductor industry continues to push the limits of sub-micron technology, the ITRS expects hardware (e.g., die-to-die, wafer-to-wafer, and chip-to-chip) variations to continue increasing over the next few decades. As a result, it is imperative for designers to build variation-aware software stacks that may adapt and opportunistically exploit said variations to increase system performance/responsiveness as well as minimize power consumption. The memory subsystem is one of the largest components in today's computing system, a main contributor to the overall power consumption of the system, and therefore one of the most vulnerable components to the effects of variations (e.g., power). This paper discusses the concept of variability-aware memory management for nanoscale computing systems. We show how to opportunistically exploit the hardware variations in onchip and off-chip memory at the system level through the deployment of variation-aware software stacks.

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Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective

Cited by 46 publications

References 25 publications

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

A Task Scheduling Scheme Considering Hybrid Main Memory and Interactive Tasks

Variability-aware memory management for nanoscale computing

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