SPICE-Only Model for Spin-Transfer Torque Domain Wall MTJ Logic

Hu, Xuan; Timm, Andrew; Brigner, Wesley H.; Incorvia, Jean Anne C.; Friedman, Joseph S.

doi:10.1109/ted.2019.2912756

Cited by 25 publications

(18 citation statements)

References 43 publications

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“…This report significantly extends early simulated work, which demonstrated a 1-bit full adder [19] by utilizing a recent SPICE model [20] to implement a complex, multibit adder system. The SPICE model has been benchmarked against and reproduces the DW behavior predicted by micromagnetic simulations.…”

Section: Introductionsupporting

confidence: 57%

“…We assume that a clock with V CLK = 125 mV is supplied by external CMOS switches with a period of 15 ns and a duration of 2 ns for each clock pulse. A wait time of 3 ns is provided between successive pulses CLK1, CLK2, and CLK3 of the three-phase clock to allow adequate time for the DWs, which possess inertia [20], to settle to their final positions. Fig.…”

Section: Dw-mtj Device and Adder Design A Dw-device And Its Varimentioning

confidence: 99%

“…2(a) shows the circuit diagram of a DW-MTJ 1-bit full adder implemented using DW NAND and buffer devices of varying fan-out (up to FO4). The full adder circuit is the same as that used in [19] and [20], but with a chain of four buffer elements replaced by four NAND gates operated as inverters. This modification allows the clock terminal of the device to always have at least one low-resistance path to ground, ensuring that each device is reset reliably.…”

Section: Dw-mtj Device and Adder Design A Dw-device And Its Varimentioning

confidence: 99%

“…Circuit-level simulations of DW-MTJ logic are enabled by SPICE models of the STT DW-MTJ devices [20] and validated by micromagnetic simulations [19] using OOMMF [32]. The SPICE models are implemented in Verilog-A and circuit simulations are performed using the Cadence Virtuoso Spectre simulator [33].…”

Section: Energy and Delay Modelingmentioning

confidence: 99%

“…We also model the temperature dependence of the MTJ tunneling resistance R p using the model in [40], assuming an oxide thickness of 1.1 nm and an energy barrier of 0.39 eV. A decrease in M sat also influences the velocity of the DWs [20]. Fig.…”

Section: E Sensitivity To Temperaturementioning

confidence: 99%

See 4 more Smart Citations

Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

Xiao

Marinella

Bennett

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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The domain-wall (DW)-magnetic tunnel junction (MTJ) device implements universal Boolean logic in a manner that is naturally compact and cascadable. However, an evaluation of the energy efficiency of this emerging technology for standard logic applications is still lacking. In this article, we use a previously developed compact model to construct and benchmark a 32-bit adder entirely from DW-MTJ devices that communicates with DW-MTJ registers. The results of this large-scale design and simulation indicate that while the energy cost of systems driven by spin-transfer torque (STT) DW motion is significantly higher than previously predicted, the same concept using spin-orbit torque (SOT) switching benefits from an improvement in the energy per operation by multiple orders of magnitude, attaining competitive energy values relative to a comparable CMOS subprocessor component. This result clarifies the path toward practical implementations of an all-magnetic processor system. INDEX TERMS Benchmarking, domain wall (DW), magnetic logic, magnetic tunnel junction (MTJ), post-CMOS logic, spintronics.

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Section: Introductionsupporting

confidence: 57%

Section: Dw-mtj Device and Adder Design A Dw-device And Its Varimentioning

confidence: 99%

Section: Dw-mtj Device and Adder Design A Dw-device And Its Varimentioning

confidence: 99%

Section: Energy and Delay Modelingmentioning

confidence: 99%

Section: E Sensitivity To Temperaturementioning

confidence: 99%

See 3 more Smart Citations

Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

Xiao

Marinella

Bennett

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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SOT-MRAM Memories for Energy Efficient Embedded and AI Applications

Singh,

Raj,

Khosla

2024

Lecture Notes in Electrical Engineering

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Nanoscale domain wall devices with magnetic tunnel junction read and write

et al. 2021

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Fast domain wall (DW) motion in magnetic nanostructures is crucial for future spintronic device concepts. However, a lack of energy-efficient, scalable and industry-relevant ways to electrically read and write DWs in nanoscale devices impedes practical applications. Here, we demonstrate that full electrical control of DW devices can be achieved by incorporating typical high DW velocity materials (i.e., Pt/Co and synthetic antiferromagnetic (SAF) Pt/Co/Ru/Co) into perpendicular magnetic tunnel junctions (pMTJs). We first show tunneling magnetoresistance (TMR) readout and efficient spin transfer torque (STT) writing, comparable to current STT-MRAM technology. Based on time-resolved measurements, we find faster STT switching dynamics in the SAF-based hybrid free layer than in conventional dual-MgO free layer while maintaining retention stability. We demonstrate the full operation of DW devices at nanoscale with MTJs enabling electrical read and write, and a heavy metal enabling spin orbit torque (SOT)-driven DW motion for information transmission. Beside implications to technology and applications, we show that these devices can be used as a tool to explore the physics of DW dynamics at nanoscale. Furthermore, using a SAFbased DW conduit has the potential to enhance device performance with faster and more reliable DW motion. This proof-of-concept offers a pathway to the technological development of highperformance and low-power DW-based devices.Magnetic domain walls (DW) could form a key ingredient in next generation logic and data storage devices [ 1,2] such as racetrack memory [ 3,4], spin logic [ 5,6,7,8] and neuromorphic computing [ 9,10,11].The discovery of high DW velocity governed by the Dzyaloshinskii-Moriya interaction (DMI) and spin-orbit torque (SOT) [ 12,13,14,15] in ultrathin magnetic layers on heavy metals, the additional exchange coupling torque (ECT) in synthetic antiferromagnetic (SAF) systems [ 16] and the angular momentum compensation in ferrimagnets [ 17], were major breakthroughs in the development of fast, high density, and low-energy devices based on DW motion. To enable these materials for practical application, DWs are required to be efficiently written and read at the nanoscale. However, to date, writing of DWs has mainly been performed through magnetic field-based approaches, and read out through either Hall bar devices or magnetic imaging techniques [ 5,8,9,12,13,17,14]. These schemes play a crucial role in characterizing material properties, but their applicability

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SPICE-Only Model for Spin-Transfer Torque Domain Wall MTJ Logic

Cited by 25 publications

References 43 publications

Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

SOT-MRAM Memories for Energy Efficient Embedded and AI Applications

Nanoscale domain wall devices with magnetic tunnel junction read and write

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