Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

Xiao, T. Patrick; Marinella, Matthew; Bennett, Christopher H.; Hu, Xuan; Feinberg, Benjamin A.; Jacobs-Gedrim, Robin; Agarwal, Sapan; Brunhaver, John; Friedman, Joseph S.; Incorvia, Jean Anne C.

doi:10.1109/jxcdc.2019.2955016

Cited by 22 publications

(12 citation statements)

References 47 publications

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“…As depicted in Fig. 6, a 4:16 triple-row decoder can be designed by interleaving four 2:4 dynamic N AN D decoders 5 . Since single-row decoding must co-exist with triple-row decoding, an address translator circuit is used to switch between the two modes using M AJ as a control signal.…”

Section: A Functional Completenessmentioning

confidence: 99%

“…As a quantitative example, [3] points out that the energy for DRAM access is 3556× the energy for 16-bit addition in 45 nm CMOS technology. Similarly, DRAM access latency is ≈ 100 ns [4], while latency of 32-bit adder is 4 ns in CMOS technology [5], implying that data movement latency forms a significant portion of computation latency in conventional von-Neumann computing model. Consequently, there had been many efforts in the last 10-15 years to combat the memory wall by bringing the processor and memory unit closer together.…”

Section: Introductionmentioning

confidence: 99%

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Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Reuben

Pechmann

2021

IEEE Trans. VLSI Syst.

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To overcome the 'von Neumann bottleneck', methods to compute in memory are being researched in many emerging memory technologies including Resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared to NAND/NOR/IMPLY logic. In this work, we propose a method to implement a majority gate in a transistoraccessed ReRAM array during READ operation. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. While many methods have been proposed recently to implement Boolean logic in memory, the latency of in-memory adders implemented as a sequence of such Boolean operations is exorbitant (O(n)). Parallel-prefix adders use prefix computation to accelerate addition in conventional CMOS-based adders. By exploiting the parallel-friendly nature of the proposed majority gate and the regular structure of the memory array, it is demonstrated how parallel-prefix adders can be implemented in memory in O(log(n)) latency. The proposed in-memory addition technique incurs a latency of 4•log(n)+6 for n-bit addition and is energy-efficient due to absence of sneak-currents in 1Transistor-1Resistor configuration.

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Section: A Functional Completenessmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Reuben

Pechmann

2021

IEEE Trans. VLSI Syst.

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“…IV. RESULTS The network was initially simulated in Cadence using models that followed DW-MTJ behavior [36]- [38]. Larger network sizes took a prohibitively long time to simulate, so a specialized simulation program was created which was able to perform the calculations significantly faster.…”

Section: Parameters 1) Mtj Parametersmentioning

confidence: 99%

High-Speed CMOS-Free Purely Spintronic Asynchronous Recurrent Neural Network

Mathews¹,

B.²,

Thayil³

et al. 2021

Preprint

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Neuromorphic computing systems overcome the limitations of traditional von Neumann computing architectures. These computing systems can be further improved upon by using emerging technologies that are more efficient than CMOS for neural computation. Recent research has demonstrated memristors and spintronic devices in various neural network designs boost efficiency and speed. This paper presents a biologically inspired fully spintronic neuron used in a fully spintronic Hopfield RNN. The network is used to solve tasks, and the results are compared against those of current Hopfield neuromorphic architectures which use emerging technologies.

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“…As noted in Tables 3 and 4, in-memory adders require tens of steps for addition operations. Even if a single step takes 5 ns (RRAMs can switch in a few ns), this would be much larger than the latency incurred in CMOS technology (32-bit addition operation can be performed in 4 ns in CMOS technology [62]). However, in in-memory arithmetic, the energy and latency (hundreds of ns) for data movement is avoided (the numbers to be added have to be moved from DRAM memory to processor in conventional approach).…”

Section: Xor B 0 a 0 B 1 A 1 B 2 A 2 B 3 A 3 B 4 A 4 B 5 A 5 B 6 A 6 mentioning

confidence: 99%

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

Reuben

2020

JLPEA

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As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.

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Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

Cited by 22 publications

References 47 publications

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

High-Speed CMOS-Free Purely Spintronic Asynchronous Recurrent Neural Network

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

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