2007
DOI: 10.1145/1255456.1255472
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Speedups in embedded systems with a high-performance coprocessor datapath

Abstract: This article presents the speedups achieved in a generic single-chip microprocessor system by employing a high-performance datapath. The datapath acts as a coprocessor that accelerates computational-intensive kernel sections thereby increasing the overall performance. We have previously introduced the datapath which is composed of Flexible Computational Components (FCCs). These components can realize any two-level template of primitive operations. The automated coprocessor synthesis method from high-level soft… Show more

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Cited by 5 publications
(1 citation statement)
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“…Galanis et al have exploited a dataflow-based approach to map different functionalities over the proposed reconfigurable computing array in [23]. In their work the host processor is connected to a co-processing unit, implemented by means of a reconfigurable datapath, where: 1) PEs are an ALU and a multiplier that can take operands from other nodes or from a register bank; and 2) the interconnection among PEs is a full crossbar (or a fat-tree network if scalability issues may arise).…”
Section: Coarse-grained and Runtime Reconfigurable Arraysmentioning
confidence: 99%
“…Galanis et al have exploited a dataflow-based approach to map different functionalities over the proposed reconfigurable computing array in [23]. In their work the host processor is connected to a co-processing unit, implemented by means of a reconfigurable datapath, where: 1) PEs are an ALU and a multiplier that can take operands from other nodes or from a register bank; and 2) the interconnection among PEs is a full crossbar (or a fat-tree network if scalability issues may arise).…”
Section: Coarse-grained and Runtime Reconfigurable Arraysmentioning
confidence: 99%