Specification and Verification of Soft Error Performance in Reliable Internet Core Routers

Silburt, A.L.; Evans, Adrian; Burghelea, A.; Wen, Shi-Jie; Ward, David; Norrish, R.; Hogle, D.

doi:10.1109/tns.2008.2001742

Cited by 13 publications

(3 citation statements)

References 14 publications

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“…To better understand the impact of soft errors and the effects of different chip level and system level mitigation strategies, we classify the SEU impact for networking system into five user-experienced outage time zones. They are: No-outage, Low Impact (Low), Medium Impact (Medium), High Impact (High) and Unrecoverable zones [2].…”

Section: System Level Mitigation Methodsmentioning

confidence: 99%

A comprehensive soft error analysis tool for core networking system

Zhu

Wong

Wen

2013

2013 IEEE International Reliability Physics Symposium (IRPS)

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In this paper, we developed a comprehensive singleevent upset (SEU) analysis tool. To achieve this goal we start by defining the SEU mitigation strategy as a combination of chip level methods and system level methods. Given a particular SEU chip level and/or system level mitigation choice, we propose first categorizing the SEU Failure In Time (FIT) into different time window bins based on SEU recovery time. Then we analyze the impact of each mitigation strategy, results in the FIT value change in each bin. This tool enables the engineers to do the SEU mitigation design in early design phase. A user-friendly Excel format is also developed to make the complicated model easy to use.The system can be modeled using the tool at an early stage to support design decisions and trade-offs related to potentially costly mitigation strategies. SEU; Reliability; Mitigation; soft errorsI.

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Section: System Level Mitigation Methodsmentioning

confidence: 99%

A comprehensive soft error analysis tool for core networking system

Zhu

Wong

Wen

2013

2013 IEEE International Reliability Physics Symposium (IRPS)

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“…Many critical bits that are used by a design will not cause functional failure if upset. The effect of some CRAM upsets may be masked by the timing, logic, and the current state of the design [24]. A soft error occurring too late in a clock cycle to be latched into memory, or an upset in a register whose value will be over written before it is used are examples of temporal masking.…”

Section: Architectural Vulnerability Factormentioning

confidence: 99%

Impact of Soft Errors on Large-Scale FPGA Cloud Computing

Keller

Wirthlin

2019

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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FPGAs are being used in large numbers within cloud computing to provide high-performance, low-power alternatives to more traditional computing structures. While FPGAs provide a number of important benefits to cloud computing environments, they are susceptible to radiation-induced soft errors, which can lead to silent data corruption or system instability. Although soft errors within a single FPGA occur infrequently, soft errors in large-scale FPGAs systems can occur at a relatively high rate. This paper investigates the failure rate of several FPGA applications running within an FPGA cloud computing node by performing fault injection experiments to determine the susceptibility of these applications to soft-errors. The results from these experiments suggest that silent data corruption will occur every few hours within a 100,000 node FPGA system and that such a system can only maintain high-levels of reliability for short periods of operation. These results suggest that soft-error detection and mitigation techniques may be needed in large-scale FPGA systems.

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“…The software layer (i.e., firmware, system and application software) is a key element of a complex digital system and plays a key role from the reliability standpoint [14]. While raw errors are generated at the technology level due to undesired effects such as ageing, environmental stress, variability etc., many detectable errors can be gracefully managed by correct software handling and a significant portion of the undetectable errors may be masked, depending on the application.…”

Section: Software Components Characterizationmentioning

confidence: 99%

RIIF-2: Toward the next generation reliability information interchange format

Savino

Carlo

Vallero

et al. 2016

2016 IEEE 22nd International Symposium on on-Line Testing and Robust System Design (IOLTS)

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1-This paper describes the joint effort of the two FP7 EU projects CLERECO and MoRV toward the definition of an extended reliability information exchange format able to manage reliability information for the full system stack, from technology up to the software level. The paper starts from the RIIF language initiative, proposing a set of new features to improve the expression power of the language and to extend it to the software layer of a system. The proposed extended reliability information exchange format named RIIF-2 has the potential to support the development of next generation reliability analysis tools that will help to fully include reliability evaluation into an automated design flow, pushing cross-layer reliability considerations at the same level of importance as area, timing and power consumption when performing design exploration for new products.

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Specification and Verification of Soft Error Performance in Reliable Internet Core Routers

Cited by 13 publications

References 14 publications

A comprehensive soft error analysis tool for core networking system

A comprehensive soft error analysis tool for core networking system

Impact of Soft Errors on Large-Scale FPGA Cloud Computing

RIIF-2: Toward the next generation reliability information interchange format

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