Sparc T4: A Dynamically Threaded Server-on-a-Chip

Shah, Mehul A.; Golla, Robert; Grohoski, Greg; Jordan, Paul L.; Barreh, J.; Brooks, Jeffrey; Greenberg, Michael; Levinsky, G.; Luttrell, M.; Olson, Charles; Samoail, Z.; Smittle, M.; Ziaja, T.

doi:10.1109/mm.2012.1

Cited by 44 publications

(22 citation statements)

References 2 publications

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“…We chose the former design as it constitutes the backbone of a number of current many-core systems, such as the Intel KNF and the Tilera TILE64 [3,28]. We envision the latter as the natural successor to in-order CMP cores, when future technology nodes will allow the integration of a larger number of transistors, but performance returns from thread-level parallelism wanes [7,29].…”

Section: Methodsmentioning

confidence: 99%

Viper: Virtual pipelines for enhanced reliability

Pellegrini¹,

Greathouse²,

Bertacco³

2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device reliability is a secondary concern. As the rate of permanent hardware faults increases, robustness will become a first class constraint for even low-cost systems. Current research into reliable architectures has focused on ad-hoc solutions to improve designs without altering their centralized control logic. Unfortunately, this centralized control presents a single point of failure, which limits long-term robustness.To address this issue, we introduce Viper, an architecture built from a redundant collection of fine-grained hardware components. Instructions are perceived as customers that require a sequence of services in order to properly execute. The hardware components vie to perform what services they can, dynamically forming virtual pipelines that avoid defective hardware. This is done using distributed control logic, which avoids a single point of failure by construction.Viper can tolerate a high number of permanent faults due to its inherent redundancy. As fault counts increase, its performance degrades more gracefully than traditional centralized-logic architectures. We estimate that fault rates higher than one permanent faults per 12 million transistors, on average, cause the throughput of a classic CMP design to fall below that of a Viper design of similar size.

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Section: Methodsmentioning

confidence: 99%

Viper: Virtual pipelines for enhanced reliability

Pellegrini¹,

Greathouse²,

Bertacco³

2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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“…Confluence relies on predecoding to generate the BTB metadata of the branches in a block before the block is inserted into the L1-I. The predecoder requires a few cycles to perform the branch scan within a cache block before the block is inserted into the L1-I [7,34]. However, this latency is not on the critical path if the block is fetched into the L1-I earlier than it is needed with the guidance of the instruction prefetcher.…”

Section: Airbtb Insertions and Replacementsmentioning

confidence: 99%

“…Today's commercial processor cores typically comprise 3-5 fetch stages followed by several decode stages [2,7,25,34]. Similarly, we model a core with three fetch stages and fifteen stages in total, representative of an ARM Cortex-A72, which has an area of 7.2mm 2 when scaled to the 40nm technology [2].…”

Section: Baseline System Configurationmentioning

confidence: 99%

“…To eliminate or mitigate the BTB storage overhead, cores with hardware multithreading [34,35] employ predecoding to scan the branches in the instruction blocks that are fetched into L1-I, precompute the target addresses of the branches, and modify the branch instructions to store the lower bits of the target address before they are inserted into the instruction cache. This way, the target address of a taken branch is formed with a simple concatenation of the branch PC and the low order bits of the target address, right after the instruction is fetched from the L1-I.…”

Section: Related Workmentioning

confidence: 99%

“…In the absence of multiple hardware threads to cover the latency, this scheme significantly hurts single-threaded performance by requiring several cycles after fetch to identify branches within a cache block and compute their targets. To mitigate the resulting fetch bubbles, some processors employ small BTBs [34]; however, such designs still expose the core to the high latency of target computation whenever the small BTB misses.…”

Section: Related Workmentioning

confidence: 99%

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Confluence

Kaynak¹,

Grot

Falsafi³

2015

Proceedings of the 48th International Symposium on Microarchitecture

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Multi-megabyte instruction working sets of server workloads defy the capacities of latency-critical instructionsupply components of a core; the instruction cache (L1-I) and the branch target buffer (BTB). Recent work has proposed dedicated prefetching techniques aimed separately at L1-I and BTB, resulting in high metadata costs and/or only modest performance improvements due to the complex control-flow histories required to effectively fill the two components ahead of the core's fetch stream.This work makes the observation that the metadata for both the L1-I and BTB prefetchers require essentially identical information; the control-flow history. While the L1-I prefetcher necessitates the history at block granularity, the BTB requires knowledge of individual branches inside each block. To eliminate redundant metadata and multiple prefetchers, we introduce Confluence -a frontend design with unified metadata for prefetching into both L1-I and BTB, whose contents are synchronized. Confluence leverages a stream-based prefetcher to proactively fill both components ahead of the core's fetch stream. The prefetcher maintains the control-flow history at block granularity and for each instruction block brought into the L1-I, eagerly inserts the set of branch targets contained in the block into the BTB. Confluence provides 85% of the performance improvement provided by an ideal frontend (with a perfect L1-I and BTB) with 1% area overhead per core, while the highest-performance alternative delivers only 62% of the ideal performance improvement with a per-core area overhead of 8%.

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2020

Microprocessor 4

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Sparc T4: A Dynamically Threaded Server-on-a-Chip

Cited by 44 publications

References 2 publications

Viper: Virtual pipelines for enhanced reliability

Viper: Virtual pipelines for enhanced reliability

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