Spara: An Energy-Efficient ReRAM-Based Accelerator for Sparse Graph Analytics Applications

Zheng, Long; Zhao, Jieshan; Huang, Yu; Wang, Qinggang; Zeng, Zhen; Xue, Jingling; Jin, Hai

doi:10.1109/ipdps47924.2020.00077

Cited by 26 publications

(17 citation statements)

References 32 publications

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“…This is particularly a challenge for the real-world graphs that often have the skewed degree distribution. To address this problem, GraphSAR [102] is proposed based on the insights that the sparsity can be adjusted with graph reordering. Still considering the matrix view of a graph, if an update of a vertex is computed using all non-zeros in a column, it is possible to "move" the non-zeros close to each other so that the subgraphs covered by the GEs become denser, thereby reducing the computation waste.…”

Section: Graphsarmentioning

confidence: 99%

Graph processing and machine learning architectures with emerging memory technologies: a survey

Qian

2021

Sci. China Inf. Sci.

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This paper surveys domain-specific architectures (DSAs) built from two emerging memory technologies. Hybrid memory cube (HMC) and high bandwidth memory (HBM) can reduce data movement between memory and computation by placing computing logic inside memory dies. On the other hand, the emerging non-volatile memory, metal-oxide resistive random access memory (ReRAM) has been considered as a promising candidate for future memory architecture due to its high density, fast read access and low leakage power. The key feature is ReRAM's capability to perform the inherently parallel in-situ matrixvector multiplication in the analog domain. We focus on the DSAs for two important applications-graph processing and machine learning acceleration. Based on the understanding of the recent architectures and our research experience, we also discuss several potential research directions.

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Section: Graphsarmentioning

confidence: 99%

Graph processing and machine learning architectures with emerging memory technologies: a survey

Qian

2021

Sci. China Inf. Sci.

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“…Hence, ReRAM-based accelerators for both DNN training and inference have been extensively studied [6] [7]. Moreover, ReRAM based graph accelerators have been shown to significantly outperform CPU-or GPU-based systems both in terms of execution time and energy [8] [14] [15]. However, these solutions focus mainly on accelerating the computation.…”

Section: A Reram-based Architecturesmentioning

confidence: 99%

“…It should be noted that even smaller ReRAM sizes can also be used for E-PEs [14]. In this work, we adopt (without any loss of generality) the 8x8 tile architecture for E-PE following recent trends [8] [15].…”

Section: A Role Of Heterogeneitymentioning

confidence: 99%

ReGraphX: NoC-enabled 3D Heterogeneous ReRAM Architecture for Training Graph Neural Networks

Arka

Doppa

Pande

et al. 2021

2021 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Graph Neural Network (GNN) is a variant of Deep Neural Networks (DNNs) operating on graphs. However, GNNs are more complex compared to traditional DNNs as they simultaneously exhibit features of both DNN and graph applications. As a result, architectures specifically optimized for either DNNs or graph applications are not suited for GNN training. In this work, we propose a 3D heterogeneous manycore architecture for on-chip GNN training to address this problem. The proposed architecture, ReGraphX, involves heterogeneous ReRAM crossbars to fulfill the disparate requirements of both DNN and graph computations simultaneously. The ReRAMbased architecture is complemented with a multicast-enabled 3D NoC to improve the overall achievable performance. We demonstrate that ReGraphX outperforms conventional GPUs by up to 3.5X (on an average 3X) in terms of execution time, while reducing energy consumption by as much as 11X.

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“…In this manner, MCA is able to perform the matrix multiplication operation in just one step. Resistive memory in its memristive crossbar array (MCA) configuration can significantly accelerate matrix multiply operations commonly found in neural network, graph, and image processing workloads [19,[82][83][84][85][86][87][88][89]. Figure 5a shows a mathematical abstraction of one such operation for a single-layer perceptron implementing binary classification, where x are the inputs to the perceptron, w are the weights to the perceptron, sgn is the signum function, and y is the output of the perceptron [90].…”

Section: Memory Typesmentioning

confidence: 99%

“…In contrast, DRAM requires multiple loads/stores and computation steps to perform the same operation. This advantage is exploited by management policies which map matrix vector multiplication to ReRAM crossbar arrays [19,[82][83][84][85][86][87][88][89].…”

Section: Energy Efficiencymentioning

confidence: 99%

A Survey of Resource Management for Processing-In-Memory and Near-Memory Processing Architectures

Khan

Pasricha

Kim

2020

JLPEA

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Due to the amount of data involved in emerging deep learning and big data applications, operations related to data movement have quickly become a bottleneck. Data-centric computing (DCC), as enabled by processing-in-memory (PIM) and near-memory processing (NMP) paradigms, aims to accelerate these types of applications by moving the computation closer to the data. Over the past few years, researchers have proposed various memory architectures that enable DCC systems, such as logic layers in 3D-stacked memories or charge-sharing-based bitwise operations in dynamic random-access memory (DRAM). However, application-specific memory access patterns, power and thermal concerns, memory technology limitations, and inconsistent performance gains complicate the offloading of computation in DCC systems. Therefore, designing intelligent resource management techniques for computation offloading is vital for leveraging the potential offered by this new paradigm. In this article, we survey the major trends in managing PIM and NMP-based DCC systems and provide a review of the landscape of resource management techniques employed by system designers for such systems. Additionally, we discuss the future challenges and opportunities in DCC management.

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Spara: An Energy-Efficient ReRAM-Based Accelerator for Sparse Graph Analytics Applications

Cited by 26 publications

References 32 publications

Graph processing and machine learning architectures with emerging memory technologies: a survey

Graph processing and machine learning architectures with emerging memory technologies: a survey

ReGraphX: NoC-enabled 3D Heterogeneous ReRAM Architecture for Training Graph Neural Networks

A Survey of Resource Management for Processing-In-Memory and Near-Memory Processing Architectures

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