Graph processing and machine learning architectures with emerging memory technologies: a survey

Abstract

This paper surveys domain-specific architectures (DSAs) built from two emerging memory technologies. Hybrid memory cube (HMC) and high bandwidth memory (HBM) can reduce data movement between memory and computation by placing computing logic inside memory dies. On the other hand, the emerging non-volatile memory, metal-oxide resistive random access memory (ReRAM) has been considered as a promising candidate for future memory architecture due to its high density, fast read access and low leakage power. The key feature is ReRAM's capability to perform the inherently parallel in-situ matrixvector multiplication in the analog domain. We focus on the DSAs for two important applications-graph processing and machine learning acceleration. Based on the understanding of the recent architectures and our research experience, we also discuss several potential research directions.

Leakage control of urban water supply network and mathematical analysis and location of leakage points based on machine learning

“…At the end of the model analysis, the server model middleware issues the simplification strategy and converts it into the instructions that can be recognized by the terminal, which is pushed to the terminal, so that the terminal has some decision-making ability, and sends an alarm in time when the terminal behavior deviates beyond the tolerance range. This will provide timely and important information on leakage detection, control and repair [12].…”

一种冗余感知的高能效图计算加速器

“…尝试提升图计算算法的访存效率. [24] 例如, Graphicionado [10] 通过将顶点数据静态缓存于片上便笺 存储器的方式, 将慢速的乱序片外访问转化为快速的乱序片上访问, 提升内存带宽利用率. Hats [25] 提出了面向图计算的顶点数据预取器, 降低内存访问延迟.…”

PhGraph: A High-Performance ReRAM-Based Accelerator for Hypergraph Applications

“…2) Limitations of ReRAM-based Graph Accelerators: Previous studies [9], [21] have demonstrated that PIM is promising in tackling the memory bottleneck arising in the traditional von Neumann architecture. The recent breakthrough achieved by ReRAM-based graph processing acceleration [9], [10] further motivates us to accelerate hypergraph processing using ReRAM-based architecture.…”

“…Processing-in-memory has shown significant superiority in accelerating memory-bound applications, such as graph processing and neural networks [9], [18], [20], [21]. Several efforts utilize ReRAM-based analog PIM to accelerate graph applications [9], [21], taking advantage of native MVM operator and high parallel in-situ processing. ReRAM-based digital PIM is a novel architecture [17], [19], which is emerging for PIM-based acceleration [18], [20], [32].…”