SPar: A DSL for High-Level and Productive Stream Parallelism

Griebler, Dalvan; Danelutto, Marco; Torquati, Massimo; Fernandes, Luiz Gustavo

doi:10.1142/s0129626417400059

Cited by 63 publications

(85 citation statements)

References 7 publications

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“…25 Another way is to focus on Domain-Specific Language (DSL) which aims representing parallelism in stream-based applications, like SPar based on C++. 26 Our work differs from the previous studies in two important aspects. First, we propose to explicitly specify the accelerator kernel as a dataflow graph, and to easily add accelerator function calls in the host code, and the data transfers.…”

contrasting

confidence: 58%

“…One way is to focus on application and domain‐specific accelerators: Neural network, Bayesian learning, bioinformatics, stencil computing, energy‐efficient accelerators for graph analytics algorithms, and irregular applications mapping . Another way is to focus on Domain‐Specific Language (DSL) which aims representing parallelism in stream‐based applications, like SPar based on C++ …”

Section: Related Workmentioning

confidence: 99%

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ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

Penha

Silva

et al. 2018

Concurrency and Computation

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Summary Dataflow‐based FPGA accelerators have become a promising alternative to deliver energy‐efficient high‐performance computing. However, FPGA programming is still a challenge. This paper presents Accelerator Design and Deploy (ADD), a high‐level framework to specify, to simulate, and to implement dataflow accelerators for streaming applications. The framework includes an open dataflow operator library, and templates are provided to easily design new operators. The framework also provides a high‐level and an accurate simulation at circuit level with short execution times. Moreover, ADD provides software and hardware APIs to simplify the integration process, extending the benefits of portability from low‐cost FPGA boards to high performance datacenter FPGA platforms. Our framework supports coupling with high‐level programming languages, and it has been validated on two FPGA platforms: the Intel high‐performance CPU‐FPGA heterogeneous computing platform and an educational FPGA kit. We show that our simple approach presents competitive performance, both in time and energy, when compared to multi‐core and GPU accelerators.

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contrasting

confidence: 58%

Section: Related Workmentioning

confidence: 99%

ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

Penha

Silva

et al. 2018

Concurrency and Computation

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“…Attempts to produce more powerful abstractions, ready-to-use by the programmer, have been made in few past works. In [26] a DSL for streaming applications has been developed using the C++11 attributes to annotate the code by introducing parallel patterns (pipelines and functional replication). GrPPi [27] is a high-level C++11 interface for writing parallel programs featuring a pattern-based approach similar to the one proposed in this paper.…”

Section: Related Workmentioning

confidence: 99%

Raising the Parallel Abstraction Level for Streaming Analytics Applications

et al. 2019

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In the stream processing domain, applications are represented by graphs of operators arbitrarily connected and filled with their business logic code. The APIs of existing Stream Processing Systems (SPSs) ease the development of transformations that recur in the streaming practice (e.g., filtering, aggregation and joins). In contrast, their parallelism abstractions are quite limited since they provide support to stateless operators only, or when the state is organized in a set of key-value pairs. This paper presents how the parallel patterns methodology can be revisited for sliding-window streaming analytics. Our vision fosters a design process of the application as composition and nesting of ready-to-use patterns provided through a C++17 fluent interface. Our prototype implements the run-time system of the patterns in the FastFlow parallel library expressing thread-based parallelism. The experimental analysis shows interesting outcomes. First, our pattern-based approach allows easy prototyping of different versions of the application, and the programmer can leverage nesting of patterns to increase performance (up to 37% in one of the two considered test-bed cases). Second, our FastFlow implementation outperforms (three times faster) the handmade porting of our patterns in popular JVM-based SPSs. Finally, in the concluding part of this paper, we explore the use of a task-based run-time system, by deriving interesting insights into how to make our patterns library suitable for multi backends. INDEX TERMS Data stream processing, streaming analytics, sliding-window queries, parallel patterns, multicore programming.

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“…A similar approach, which leverages the new C++1x features, consists of annotating the sequential code with C++ attributes to introduce parallel patterns in specific regions of code (usually compute-intensive kernels). Then, a source-to-source compiler is responsible for translating the annotated C++ code into a parallel code linked to the proper pattern-based runtime library [20,37].…”

Section: Parallel Pattern-based Approachesmentioning

confidence: 99%

“…Some of these frameworks, such as P 3 L [5], ASSIST [57], and SAC [36], provide a new language used to introduce pattern abstractions already in the early phases of the software development process. More recent approaches like FastFlow [22], SkePU [32], GrPPI [26], SPar [37], and PACXX [38], rely on new features of modern C++ language. Patterns are introduced by instantiating class objects at any place in the code or by using suitable C++11 attributes as in SPar.…”

Section: Examples Of Parallel Pattern-based Codementioning

confidence: 99%

Bringing Parallel Patterns Out of the Corner

Sensi

Matteis

Torquati

et al. 2017

ACM Trans. Archit. Code Optim.

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High-level parallel programming is an active research topic aimed at promoting parallel programming methodologies that provide the programmer with high-level abstractions to develop complex parallel software with reduced time to solution. Pattern-based parallel programming is based on a set of composable and customizable parallel patterns used as basic building blocks in parallel applications. In recent years, a considerable effort has been made in empowering this programming model with features able to overcome shortcomings of early approaches concerning flexibility and performance. In this article, we demonstrate that the approach is flexible and efficient enough by applying it on 12 out of 13 PARSEC applications. Our analysis, conducted on three different multicore architectures, demonstrates that pattern-based parallel programming has reached a good level of maturity, providing comparable results in terms of performance with respect to both other parallel programming methodologies based on pragma-based annotations (i.e., OpenMP and OmpSs) and native implementations (i.e., Pthreads). Regarding the programming effort, we also demonstrate a considerable reduction in lines of code and code churn compared to Pthreads and comparable results with respect to other existing implementations. We extended this work by (i) modeling and implementing an additional seven applications by using parallel patterns (there were five in Danelutto et al. [21]), (ii) implementing four of these applications with another framework (SkePU), (iii) comparing our approach to the OmpSs programming model, (iv) adding other programmability metrics to our analysis, and (v) testing our work on two additional and completely different architectures.

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SPar: A DSL for High-Level and Productive Stream Parallelism

Cited by 63 publications

References 7 publications

ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

Raising the Parallel Abstraction Level for Streaming Analytics Applications

Bringing Parallel Patterns Out of the Corner

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