SON (Silicon on Nothing) MOSFET using ESS (Empty Space in Silicon) technique for SoC applications

Sato, Taichiro; Nii, H.; Hatano, Masayuki; Takenaka, Kazuhiro; Hayashi, H.; Ishigo, Kazutaka; Hirano, Tomotaka; Ida, K.; Aoki, Naofumi; Ohguto, T.; Ino, Kazuide; Mizushima, Ichiro; Tsunashima, Takanori

doi:10.1109/iedm.2001.979637

Cited by 8 publications

(4 citation statements)

References 2 publications

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“…In the work [5], an improved SOI-like architecture called silicon on nothing (SON) capable of SCE and DIBL suppression [6] has been integrated onto the existing ISE devices, which have already been conferred [7] for their potential for curbing SCEs-particularly punchthrough effect, along with dual material gate (DMG) architecture incorporation to overcome electron transport inefficiency [8]. The SON architecture combines the advantage of FD MOSFETs like excellent subthreshold slope, mobility, no floating body effect, etc.…”

Section: Discussionmentioning

confidence: 99%

Hot‐carrier reliability monitoring of DMG ISE SON MOSFET for improved analog performance

Kaur

Chaujar

Saxena

et al. 2010

Micro & Optical Tech Letters

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It is evident that there is a shift of less than 4% in all cases between measured results reported in [14] with open/short circuits and theory (model), and a much larger shift (15-25%) between measured results with diodes and those with open/short circuits. This means that there are two mechanisms taking part to this drift, which sum to each other. The first is the unavoidable over-etching of the metal (affecting both cases; open/short and diodes), the second is the parasite capacitance associated with the diodes package (SMD metal pads), beside those aforementioned. This drift is frequency dependent and seems to validate the above hypothesis. All these factors may be neglected in a first design iteration and considered afterward once the location of the transmission zeros have been found by means of the aforeintroduced slotline theory. Eventually, the effect of the diodes can be considered for a final tuning of the structure. It should be clear that these reported results are obtained with a single iteration, and no redesign has been done.ABSTRACT: The hot-carrier reliability, analog, and linearity characteristics of DMG ISE SON MOSFET have been discussed. The device reduces electron temperature by 35.85% in comparison to a 770 non-dual material gate (DMG) architecture showing its self-heating resistant nature. The analog performance and linearity metrics-g m /I DS , R out , V EA , and g m /g d and VIP 2 and VIP 3 -have been studied facilitating the selection of bias point for improved RF/analog performance.ABSTRACT: In this article we reported, for the first time, a low complexity Field Programmable Gate Array solution for integrating video surveillance into RFID units. The method is comprised of two major building blocks, namely a RFID transmitter operating at a maximum bandwidth of 250 kbps, and a near computation free image Figure 7 (a) Simulated VIP 2 variation with gate bias (V GS ) for different structures under consideration. L 1 ¼ 50 nm, T film ¼ 30 nm, qU M1 ¼ 4.77 eV, qU M2 ¼ 4.10 eV, and V DS ¼ 0.5 V. (b) Simulated VIP 3 variation with gate bias (V GS ) for different structures under consideration. L 1 ¼ 50 nm, T film ¼ 30 nm, qU M1 ¼ 4.77 eV, qU M2 ¼ 4.10 eV, and V DS ¼ 0.5 V

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Section: Discussionmentioning

confidence: 99%

Hot‐carrier reliability monitoring of DMG ISE SON MOSFET for improved analog performance

Kaur

Chaujar

Saxena

et al. 2010

Micro & Optical Tech Letters

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“…The other is to decrease the dielectric constant of the buried layer without increasing the parasitic capacitance between the source/drain and the substrate. Therefore, silicon-on-void (SOV) MOSFET will be a better choice to suppress the SCE caused by the potential coupling between the source and drain through the buried layer of SOI MOSFET [8][9][10][11]. Moreover, the manufacture of the SOV device structure can be basically compatible with the conventional CMOS fabrication [8][9][10].…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, silicon-on-void (SOV) MOSFET will be a better choice to suppress the SCE caused by the potential coupling between the source and drain through the buried layer of SOI MOSFET [8][9][10][11]. Moreover, the manufacture of the SOV device structure can be basically compatible with the conventional CMOS fabrication [8][9][10]. Therefore, the SOV device structure has great potential as a novel device structure in the nanoscale regime.…”

Section: Introductionmentioning

confidence: 99%

Scaling capability improvement of silicon-on-void (SOV) MOSFET

Tian

et al. 2004

Semicond. Sci. Technol.

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In this paper, the scaling capability improvement of silicon-on-void (SOV) MOSFET is comprehensively investigated. The results show that SOV MOSFET shows a significant improvement in the suppression of the short-channel effects (SCE) caused by the potential coupling between the source and drain through the buried layer. In addition, the parasitic capacitance between the source/drain and the substrate can be greatly decreased. The minimal channel length of SOV MOSFET is reduced by 27% compared with ultra-thin-body (UTB) SOI MOSFET. Most of all, the limitation of silicon film thickness of SOV MOSFET can be relaxed to about 50%, in comparison with SOI MOSFET. SOV MOSFET can alleviate the critical problem and further improve the immunity of SCE of UTB SOI MOSFET in the nanoscale regime. SOV MOSFET will be a good choice of device structure to put off the eventual limit in scaling down.

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“…Moreover, it is difficult to obtain the silicon layer with defect-free crystalline quality due to the ion-implantation damage or the defects occur during the epitaxial growth. Recently, a silicon-on-nothing (SON) transistor, which has a void under the transistor region, has been proposed as one of the ideal structure of SOI, because the dielectric constant at the region below the transistors could be with this structure [6][7][8][9][10][11][12][13][14]. SON structure was originated from the capability of selectively removing SiGe alloys against Si.…”

Section: Introductionmentioning

confidence: 99%

Selective Chemical Wet Etching of Si_0.8Ge_0.2/Si Multilayer

Kil¹,

Yang²,

Kang³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-We investigate the effect of the ageing time and etching time on the etching rate of SiGe mixed etching solution, namely 1 vp HF (6%), 2 vp H 2 O 2 (30%) and 3 vp CH 3 COOH (99.8%). For this etching solution, we found that the etch rate of SiGe layer is saturated after the ageing time of 72 hours, and the selectivity of Si 0.8 Ge 0.2 layer and Si layer is 20:1 at ageing time of 72 hours. The collapse was appeared at the etching time of 9min with etching solution of after saturation ageing time.

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SON (Silicon on Nothing) MOSFET using ESS (Empty Space in Silicon) technique for SoC applications

Cited by 8 publications

References 2 publications

Hot‐carrier reliability monitoring of DMG ISE SON MOSFET for improved analog performance

Hot‐carrier reliability monitoring of DMG ISE SON MOSFET for improved analog performance

Scaling capability improvement of silicon-on-void (SOV) MOSFET

Selective Chemical Wet Etching of Si_0.8Ge_0.2/Si Multilayer

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SON (Silicon on Nothing) MOSFET using ESS (Empty Space in Silicon) technique for SoC applications

Cited by 8 publications

References 2 publications

Hot‐carrier reliability monitoring of DMG ISE SON MOSFET for improved analog performance

Hot‐carrier reliability monitoring of DMG ISE SON MOSFET for improved analog performance

Scaling capability improvement of silicon-on-void (SOV) MOSFET

Selective Chemical Wet Etching of Si0.8Ge0.2/Si Multilayer

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Product

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Selective Chemical Wet Etching of Si_0.8Ge_0.2/Si Multilayer